Blitter support for VIDC1/20 and palette changes
Posted: Fri Feb 07, 2014
Code that requires changing to support these are detailed below. Note that all VIDC1 register writes are translated to VIDC20 registers, so we only need to take account of VIDC20 values. The latest code is in /development/32bit/cpu on the dev site.
adffs.vectors.DA2_frame_buffer
blit_DA2_frame: sets up the following registers, then calls _1bit_mode, _2bit_mode, _4bit_mode or _8bit_mode to do the blit:
R0 - MEMC_Vinit
R1 - start of GPU framebuffer
R2-R11 - free to use by the blitting code
R12 - Palette table (256 words, containing a converted palette value ready to write to the GPU framebuffer)
other variables of use, which can be loaded/pre-setup as required:
MEMC_Vstart
MEMC_Vend
vidc20_regs (table of VIDC20 registers)
IOC_ticks_per_raster IOC clock ticks per raster
HAL_vidc_list (VIDC type 3 list as passed by GraphicsV 2)
To access VIDC20 registers, setup a pointer register as follows:
and then load the registers via:
Timers
IOC_ticks_per_raster should be set at the start of the frame blit to the numer of IOC clock ticks per raster.
IOC_timers should be called at the start of each raster, R4-R6 are corrupted on return.
NOTE: In adffs.aborts.ioc_abort IOC_timers - uncomment the IOC_ticks_per_raster code.
adffs.vectors.DA2_frame_buffer
blit_DA2_frame: sets up the following registers, then calls _1bit_mode, _2bit_mode, _4bit_mode or _8bit_mode to do the blit:
R0 - MEMC_Vinit
R1 - start of GPU framebuffer
R2-R11 - free to use by the blitting code
R12 - Palette table (256 words, containing a converted palette value ready to write to the GPU framebuffer)
other variables of use, which can be loaded/pre-setup as required:
MEMC_Vstart
MEMC_Vend
vidc20_regs (table of VIDC20 registers)
+0 = HCR
+4 = HSWR
..
+88 = VCSR
+92 = VCER
IOC_registers (table of IOC registers, 1 byte per register)
+4 = HSWR
..
+88 = VCSR
+92 = VCER
+0 = IOC register 0
+1 = IOC register 1
..
+31 = IOC register 31
T1_value current value of T1 timer+1 = IOC register 1
..
+31 = IOC register 31
IOC_ticks_per_raster IOC clock ticks per raster
HAL_vidc_list (VIDC type 3 list as passed by GraphicsV 2)
+20 = physical screen width (which will be rounded up to the next 32 pixel boundary)
+44 = physical screen height
_1bit_mode, _2bit_mode, _4bit_mode, _8bit_mode: must exit via _exit and need to take account of the VIDC20 parameters, MEMC Vend/Vstart and must call IOC_timers (which corrupts R4-R6) before starting and then every four pixels or per raster (TBC).+44 = physical screen height
To access VIDC20 registers, setup a pointer register as follows:
Code: Select all
ADR R11, vidc20_regs - (VIDC20_HCR << 2)Code: Select all
LDR R2, [R11, #VIDC20_<register name> << 2]
eg.
ADR R11, vidc20_regs - (VIDC20_HCR << 2)
LDR R2, [R11, #VIDC20_HDSR << 2]Timers
IOC_ticks_per_raster should be set at the start of the frame blit to the numer of IOC clock ticks per raster.
IOC_timers should be called at the start of each raster, R4-R6 are corrupted on return.
NOTE: In adffs.aborts.ioc_abort IOC_timers - uncomment the IOC_ticks_per_raster code.