Vector writes

Discuss development specific to the Pi version of ADFFS
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JonAbbott
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Vector writes

Post by JonAbbott »

Whilst looking into why Lemmings hangs, I've realised code that takes over vectors directly is going to be an issue. In the case of Lemmings it reads/writes &100 to take over IRQv.

The write is okay as it's hypervised, the read however is a problem as it will cause the code to exit into the OS instead of the hypervised entry point.

I can think of a few ways around this:

1. Take over every vector that's likely to be written too directly. The main issue with this, is that it relies of the vector being in the same zero page location, so isn't really future proof
2. Prevent read access to page zero in non-privileged CPU modes. However, this will rely on all code executing in User mode, which is the ultimate aim but currently not the case and will require careful management of aborts generated outside of the JIT
3. Map in our own memory map. This is the obvious choice and is the method we'd require for a full hypervisor, although won't really work unless RISCOS is made hypervisor aware
4. Hypervise all memory reads. This will have a large impact on games, as they tend to read heavily from memory
5. Emulate instructions on first pass and target problematic ones. This obviously means coding a full CPU emulator and isn't necessary guaranteed to work where code loops
6. Manually find the vector exit instruction and replace with MOV PC,R14 or LDR PC,[R13],#4. JITMEMORYA was added for just this sort of thing so this is a trivial workaround to implement

2/6 are the only viable choices. For the time being I'll use method 6 as I don't think the number of games that directly write to vectors is that high, OS_ClaimDeviceVector was available in RO3 so it's only games written earlier that Palette swap that are likely to be affected.
JonAbbott
Posts: 2938
Joined: Thu Apr 11, 2013 12:13 pm
Location: Essex
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Re: Vector writes

Post by JonAbbott »

Another example is Lotus Turbo Challenge which takes over the IRQ processor vector at &18 and presumes the existing instruction is B <address>

Post RO3.1x the instruction at &18 is LDR PC, <address>. For RO3.5 thru 4.x ADFFS now changes the instruction at &18 to B <address> whilst the screen is remapped, although I've not tested any games to see if this fixes any.
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