steve3000 wrote:Have you been able to test on other RISC OS 5 hardware?
Not yet, I've been trying to get the Iyonix fixed since Dec so 1. Can get ADFFS500 working on it and 2. Have something other than the Pi to cross check against.
Getting ADFFS500 to work will be fun, in theory it should already work as it's using standard SWI's and OS features, but it's the minor differences in RISCOS across platforms that usually break it. Which reminds me, I need to test ADFFS400 on RISCOS5 IOMD and see what's broken.
I changed the code yesterday (extASM500236f), so instead of the T1 code clearing the IRQ as soon as it's raised, it leaves it until the user code clears it via a write to IRQA clear. That's changed the random crash to a predictable hang that always happens at the same time, so it's definitely the HAL timer call causing the problem and is possibly timing related.
I'm going to try stopping the Timer when the IRQ fires to see what difference that makes and only restart it when IRQA clear is written too. It will make the Timer somewhat random, but worth trying to see if it changes the hang although from Jeffrey's description it sounds like the hang may be caused by another (non-Timer) IRQ firing before the Device IRQ is cleared. The are however two IRQ's to clear, the Device IRQ (which I hope is causing the hang) and the Timer IRQ which I don't really understand and hope simply prevents the Timer from raising an IRQ again.