JIT Phase 2

Discuss development specific to the Pi version of ADFFS
JonAbbott
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Re: JIT Phase 2

Post by JonAbbott »

JonAbbott wrote:I've noticed another issue with RO4/SA which I need to fix - the screen caching isn't being passed onto the OS when it's enabled.
Fixed that and found that although it works, writes to 1F88000+ aren't appearing on the screen. Looks like it's mapping the wrong part of the display memory to 1F88000.

Oddly there's a difference between physical and virtual, on virtual it crashes when trying to write to 1FD8000 and yet works on physical.

Zarch has been running for several hours in auto-play on the Pi, so that looks okay at least.
JonAbbott
Posts: 2938
Joined: Thu Apr 11, 2013 12:13 pm
Location: Essex
Contact:

Re: JIT Phase 2

Post by JonAbbott »

Cache flushing issues on StrongARM have raised their ugly head again. To add support for FPU instructions I've had to specifically test for them before passing the vector onto RISC OS, as Undefined Instruction Aborts are being raised for instructions it's previously handled and flushed back to memory.

To be more accurate, the issue is either the write buffer or instruction cache not flushing. The data cache is definitely clear as ADFFS reads 16KB of RAM when it exits the JIT.

At a guess
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