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Magic Pockets zip still appears to be broken (as is the regular Chuck Rock zip). I'm not sure if it's just a flaky server issue or whatever, but yeah, thought I'd let Jon know. They're all corrupt again, this is starting to seriously annoy me now. I'll have to pull the site until I can either find ...

I've noticed Jet Fighter's palette is wrong since implementing mid-frame palette change support, although I'm not sure if it's directly related as I've not tested it for a few weeks. Going by the odd things going on at the bottom of the screen with what look like raster bars, I'd say it's changing t...

Cache flushing issues on StrongARM have raised their ugly head again. To add support for FPU instructions I've had to specifically test for them before passing the vector onto RISC OS, as Undefined Instruction Aborts are being raised for instructions it's previously handled and flushed back to memor...

I've now implemented sub-pages* in the JIT which has reduced the number of Aborts quite substantially in some games. Zarch for example has reduced by 75%. Before coding this I noticed Zarch was generating substantially more Aborts than it was in the early betas. Up from 10,000 / sec to 65,000 / sec,...

Emulation of the IRQ processor vector, IRQ1V vector, IOC T1 and IOC VSync pulse is now complete however there's still some general debugging of ADFFS to do: 1. StrongARM is completely broken, all games lock up solid. The games are working under emulation, so must cache related 2. James Pond now load...

Another example is Lotus Turbo Challenge which takes over the IRQ processor vector at &18 and presumes the existing instruction is B <address> Post RO3.1x the instruction at &18 is LDR PC, <address>. For RO3.5 thru 4.x ADFFS now changes the instruction at &18 to B <address> whilst the sc...

Whilst I recode the IOC emulation to get IRQ (&18) and IRQ1v (&100) to go through the JIT, extASM237c is the last version of ADFFS that will run James Pond. It's taking a bit longer than I thought to add support for these, mainly due to other changes having a knock on effect, but it's gettin...

Whilst looking into why Lemmings hangs, I've realised code that takes over vectors directly is going to be an issue. In the case of Lemmings it reads/writes &100 to take over IRQv. The write is okay as it's hypervised, the read however is a problem as it will cause the code to exit into the OS i...

Steve, it's occurred to me that we'll need to pre-stage the VIDC20 registers on the Pi on a MODE change, otherwise the blitter is going to fail once it's recoded to account for VIDC parameters. There's a few ways of doing that off the top of my head: 1. A similar botch to what I did for the current ...

Although it's currently decreasing T1 every 4 pixels, that was just a botch to save me recoding the blitter. Unless there's a requirement for per-pixel accuracy it could be changed to reduce T1 per raster. Either way, it needs to calculate the number of IOC clock ticks per pixel/raster based on the ...