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I've changed the code to set the timer value if there's a write to either T1 latch low/high or GO. That didn't make any difference however, so I then disassembled the Krisalis code. After claiming the device via OS_ClaimDeviceVector, it enables the IRQ in IRQA mask. At no point does it write to T1 l...

Option 3 Extend the master palette table. The first word contains the start raster no, followed by N AABBGGRR entries and a -1 terminator. When the palette changes mid-frame another palette table is written, so -1 becomes the start raster, followed by N AABBGGRR entries and a -1 terminator. N being...

Great, if we can decide how we want the raster palette table(s) to look, I'll make a start on the changes to adffs.aborts.vidc1_abort / vidc20_abort as they're closely tied in with the IOC code I'm currently working on...calculating the timing etc. Option 1 A 16 word table per raster, with SSBBGGRR ...

So on that basis - for IOC emulation, it's probably best to trigger the timer to start as soon as you've received the first T1 latch high and T1 latch low write. If you then receive a subsequent 'Go', reset the timer to the latch value. That explains the missing GO write then. I'll move the code th...

in the back of my mind I thought that ADFFS cached the VIDC1 writes for translation, and fired them off together to VIDC20 at the same time? This would be slightly different behaviour. But we'll see if it works soon enough... What I normally do when hijacking RISC OS code, is to look at the origina...

I've coded IOC Timer 1 (device 6), Vsync (device 3) and the IRQv emulator. Could someone confirm my understanding of how IOC Timer 1 works: 1. T1 Latch Low / High are written with the timer value 2. Bit 6 of IRQA mask is set to enable the IRQ 3. T1 Go is written to start the timer 4. IRQ is raised I...

Code that requires changing to support these are detailed below. Note that all VIDC1 register writes are translated to VIDC20 registers, so we only need to take account of VIDC20 values. The latest code is in /development/32bit/cpu on the dev site. adffs.vectors.DA2_frame_buffer blit_DA2_frame : set...

But the CallBack might be a problem. If LCDgm responds to the Service_ModeChanged by immediately patching the VIDC20 registers, this will happen before ADFFS has sent through the VIDC1 translations (which happens after the mode change has completed and control has returned to ADFFS), so ADFFS will ...

steve3000 wrote:I suspect you've done this to ensure LCDgm switches on when running on VIDC20 machines? However it shouldn't issue this command on pre-RiscPC computers, as there is no need since LCDGameModes switches on automatically on MonitorType 3 and 4.

That is why I added it, I'll correct it in the next beta.

Ok, this can be done, but there is a real probability that the behaviour will be different to as it is now, since we'll have LCDgm updating VIDC20 registers in response to Service_ModeChanged, which may be at different times to ADFFS doing its VIDC1->VIDC20 translation. So I really need to understa...