;vector_handler_1A
;-----------------
;OS_UpdateMEMC

; R11 - pointer to VARS

.vector_handler_1A
 BL      check_taskID			;is the task supported?
 BLEQ    check_SWI_in_appspace_or_JIT
 BNE     vector_handler_forward		;NO, hand to OS

 STMFD   R13!, {R2-R4, R7}
 MOV     R4, R1				;store mask for update on exit

 ADD     R7, R11, #MEMC_registers - VARS	;R7=MEMC register table
 LDR     R3, [R7, #MEMC_CR << 2]	;R3=current MEMC register value
 AND     R0, R0, R1			;R0 AND R1
 MVN     R2, #0
 EOR     R1, R1, R2			;NOT R1
 AND     R3, R3, R1			;oldMEMC AND NOT R1
 ORR     R0, R3, R0			;(oldMEMC AND NOT R1) OR (R0 AND R1)

 #if compile_IOMD == 1
   LDR     R2, [R11, #IOMD_addr - VARS]		;R2 = IOMD chip address
 #endif
 MOV     R3, #MEMC_CR
 BL      update_MEMC			;perform the write

 LDR     R0, [R7, #MEMC_CR << 2]
 BIC     R0, R0, #%111111111 << 17		;clear MEMC register
 ORR     R0, R0, #&3600000 + (MEMC_CR << 17)	;add in MEMC addr and CR reg
 ADD     R2, R11, #MEMC_mask - VARS
 LDR     R1, [R2, #0]
 STR     R4, [R2, #0]
EXITSWI "R2-R4, R7"
