;vector_handler_6E
;------------------
;reset JIT space if applicable

.vector_handler_6E
 BL      check_JIT_and_taskID		;is the task supported?
 BNE     vector_handler_forward		;NO, hand to OS

 CMP     R2, #jit_appspace_end
 BHI     vector_handler_forward

 TST     R0, #%1			;all memory?
 BEQ     _full_sync			;YES

 STMFD   R13!, {R2, R4}
 SUB     R4, R2, R1			;NO,  size - 4
 ADD     R4, R4, #4			;correct size
 MOV     R2, R1				;start address
 ADD     R11, R2, R4
 CMP     R11, #jit_appspace_end
 RSBHI   R4, R2, #jit_appspace_end	;cap end address

 CMP     R4, #0				;is it valid
 BLE     _pass_on			;NO, pass to OS
 CMP     R2, #jit_appspace_end		;within App space?
 BLLO    hv_reset_memory_block		;YES, reset JIT space
 LDMFD   R13!, {R2, R4}
 B       _exit

 ._pass_on
 LDMFD   R13!, {R2, R4}			;NO
 B       vector_handler_forward		; |+ pass to OS

._full_sync
 ADR     R12, VARS
 LDR     R11, [R12, #JIT_ARM4 - VARS]
 TEQ     R11, #1			;ARMv4 with Cache ON?
 BNE     vector_handler_forward		;NO, pass to OS

 STMFD   R13!, {R0-R9}

 MRS     R9, CPSR
 ORR     R0, R9, #%11 << 6		;need to disable all IRQ/FIQ
 MSR     CPSR_c, R0

 LDR     R1, branch_to_jit		;instruction to enter JIT
 MOV     R2, R1
 MOV     R4, R1
 MOV     R5, R1
 MOV     R6, R1
 MOV     R7, R1
 MOV     R8, R1
 MOV     R0, R1
 MOV     R3, #jit_code_start
 ADD     R3, R3, #page_zero_FIQ			;reset FIQ @ &1C-&100
 STMIA   R3!, {R0-R2, R4-R8}
 STMIA   R3!, {R0-R2, R4-R8}
 STMIA   R3!, {R0-R2, R4-R8}
 STMIA   R3!, {R0-R2, R4-R8}
 STMIA   R3!, {R0-R2, R4-R8}
 STMIA   R3!, {R0-R2, R4-R8}
 STMIA   R3!, {R0-R2, R4-R8}
 STMIA   R3!, {R0-R2}

 MOV     R3, #jit_code_start
 ADD     R3, R3, #page_zero_Scratch_Space	;reset &4000-WimpSize
 LDR     R11, [R12, #pre_JIT_wimp_slot_size - VARS]
 ADD     R11, R11, #jit_code_start + &8000
 ._L2
   STMIA   R3!, {R0-R2, R4-R8}
   STMIA   R3!, {R0-R2, R4-R8}
   STMIA   R3!, {R0-R2, R4-R8}
   STMIA   R3!, {R0-R2, R4-R8}
   CMP     R3, R11
 BLO     _L2

 MOV     R3, #jit_RMA_heap
 LDR     R11, [R3, #Heap_BaseOffset]		;illegal read of heap base
 ADD     R3, R3, #jit_code_start
 ADD     R11, R11, R3
 MOV     R14, #(jit_26bit_exits - jit_26bit_exit_size) AND NOT (128-1)
 CMP     R11, R14				;ensure we don't overwrite
 MOVHI   R11, R14				;..jit_26bit_exits
 ._L3
   STMIA   R3!, {R0-R2, R4-R8}			;fill 128 instructions
   STMIA   R3!, {R0-R2, R4-R8}
   STMIA   R3!, {R0-R2, R4-R8}
   STMIA   R3!, {R0-R2, R4-R8}
   CMP     R3, R11
 BLO     _L3

 LDR     R5, [R12, #first_codelet - VARS]
 #if compile_RO == 500
   PLD     [R5, #0]				;preload codelet header
 #endif
 ._L0
   MOV     R8, R5
   LDR     R5, [R5, #codelet_struct.next]
   #if compile_RO == 500
     PLD     [R5, #0]				;preload codelet header
   #endif
   LDR     R1, [R8, #codelet_struct.source]
   ADD     R2, R8, #codelet_struct.codelet - 8
   TEQ     R1, #0				;is it immortal?
   BLNE    free_codelet				;NO
   CMP     R5, R8				;last codelet?
 BLO     _L0					;NO

 ADR     R0, MMUControl_ARMop7
 MOV     R14, PC
 LDR     PC, [R0, #0]				;IMB full

 MSR     CPSR_c, R9				;reset IRQ/FIQ
 #if compile_IOMD == 1
   NOP
 #endif
 LDMFD   R13!, {R0-R9}

 ._exit
EXITSWI ""
