;Entry:
;R0  = instruction
;R7  = original instruction address + 8
;R14 = re-interpreted instruction address + 8

;SWP{B}  Rd, Rm, [Rn]
ALIGN   32, 4
.i_SWP
 CODELET 8

 AND     R1, R0, #%1111 << 12		;R1=Rd (destination)
 AND     R2, R0, #%1111 << 16		;R2=Rn (base)
 AND     R3, R0, #%1111			;R3=Rm (source)
 AND     R0, R0, #1 << 22		;B or W

 LDR     R4, _codelet			;1st instruction
 ORR     R4, R4, R3, LSL #12		;STR Rm, ...
 ORR     R4, R4, R0
 LDR     R5, _codelet + 4		;2nd instruction
 ORR     R5, R5, R1			;LDR Rd,
 ORR     R5, R5, R2			;LDR Rd, [Rn, #0]
 ORR     R5, R5, R0
 STMIA   R6!, {R4, R5}
 LDR     R4, _codelet + 8		;3rd instruction
 ORR     R4, R4, R1			;STR Rd, ...
 ORR     R4, R4, R0
 LDR     R5, _codelet + 12		;4th instruction
 ORR     R5, R5, R3, LSL #12		;LDR Rm, ...
 ORR     R5, R5, R0
 STMIA   R6!, {R4, R5}
 LDR     R4, _codelet + 16		;5th instruction
 ORR     R4, R4, R3, LSL #12		;STR Rm,
 ORR     R4, R4, R2			;STR Rm,[Rn]
 ORR     R4, R4, R0
 LDR     R5, _codelet + 20		;6th instruction
 ORR     R5, R5, R3, LSL #12		;LDR Rm, ...
 ORR     R5, R5, R0
 STMIA   R6!, {R4, R5}
 LDR     R4, _codelet + 24		;7th instruction
 ORR     R4, R4, R1			;LDR Rd, ...
 ORR     R4, R4, R0
 STR     R4, [R6], #4

 LDR     R3, _codelet + 28		;8th instruction
 SUB     R5, R14, R6
 SUB     R5, R5, #8 + 4			;correct for offset and prefetch
 BIC     R5, R5, #%111111 << 26
 ORR     R3, R3, R5, LSR #2		;B <original address + 4>

 STR     R3, [R6], #4
B       i_instruction_handled


 ._codelet
 STR     R0, _codelet - 4		;STR Rm
 LDR     R0, [R0, #0]			;LDR Rd,[Rn]
 STR     R0, _codelet - 8		;STR Rd
 LDR     R0, _codelet - 4		;LDR Rm
 STR     R0, [R0, #0]			;STR Rm,[Rn]
 LDR     R0, _codelet - 4		;LDR Rm
 LDR     R0, _codelet - 8		;LDR Rd
 DCD     B_blank			;R2 B <original address + 4>

