#set dbg_pause_default		= 100		;VSync pause on debug info
#set JIT_max_instructions	= 128		;max instr. to process
#set JIT_branch_prediction_max	= 8		;max B/BL to predict (must
						;be a power of 2 (2,4,8 etc)
#set JIT_SWI_OS_Flag		= 8 << 20	;OS we're going to use for
						;  hypervized SWI's
#if compile_RO == 400
  #set c32bit			= 0 << 4	;IOMD below RO5 needs 26bit
#endif
#if compile_RO > 400
  #set c32bit			= 1 << 4	;32bit mode for 32bit OS's
#endif

#set UND_exit_PC		= 8 * 4		;location on stack of exit PC
#set PC_reg			= 15		;PC register
#set PC_reglist			= 1 << 15	;PC register in LDM/STM
#set OP_condition		= %1111 << 28	;ARM OP condition bits
#set OP_AL			= %1110 << 28	;ARM AL condition

.branch_to_jit  MRC P8, 0, R0, C0, C0	;hypercall to enter JIT
.branch_to_jit_no_condition DCD 0	;hypercall to enter JIT << 4
#if JIT_cache_consistency == 1
 .JIT_inconsistent	MRC P8, 0, R0, C0, C1
#endif
#if JIT_trap_pz_code == 1
 .JIT_pz_code		MRC P8, 0, R0, C0, C2
#endif

#if compile_DEBUG == 1 AND JIT_debug == 1
 .breakpoint		DCD jit_code_start - 4
#endif
#if JIT_debug == 1 AND JIT_dump_crash == 1
 .breakpoint_dump	DCB "hostfs::0.$.dump", 0
			ALIGN
#endif




;Undefined_Instruction_Vector
;----------------------------
;entry point for JIT
;
;Entry:
; R14	- instruction address + 4
; SPSR	- original CPU mode

 ALIGN   32, 4
.Undefined_Instruction_Vector
 CMP     R14, #jit_slotsize		;in Application Space?
 BHI     pass_to_existing_UndInstr	;NO, pass call on
 CMP     R14, #jit_appspace_end		;in JIT Application Space?
 BLO     pass_to_existing_UndInstr	;NO, pass call on

					;---------------------------------
					;CHECK FOR COPRO INSTRUCTIONS
 STMFD   R13!, {R0-R1}
 LDR     R0, [R14, #-4]!		;get instruction and correct pre-fetch
 #if JIT_cache_consistency == 1
   LDR     R1, JIT_inconsistent
   TEQ     R0, R1
   BEQ     JIT_cache_inconsistent
 #endif
 #if JIT_trap_pz_code == 1
   LDR     R1, JIT_pz_code
   TEQ     R0, R1
   BEQ     JIT_page_zero_code
 #endif

 LDR     R1, branch_to_jit_no_condition	;JIT entry instruction
 TEQ     R1, R0, LSL #4			;is it a JIT entry?
 LDMFD   R13!, {R0-R1}
 BNE     pass_to_existing_UndInstr_2	;NO, Copro then, pass call on
					;---------------------------------
 STMFD   R13!, {R0-R7, R14}		;[R13, #UND_exit_PC] = R14

 SUB     R7, R14, #jit_code_start	;R7=original address
 CMP     R7, #page_zero_Scratch_Space
 BGT     _address_ok
 TEQ     R7, #page_zero_Undefined
 TEQNE   R7, #page_zero_IRQ
 BEQ     _address_ok
 CMP     R7, #page_zero_IRQ1V
 BGT     JIT_report_illegal_address	;ADFF5013
 CMP     R7, #page_zero_IRQ
 BLO     JIT_report_illegal_address	;ADFF5013

 ._address_ok
 #if JIT_debug == 1
   LDR     R1, jit_last_instrR
   SUB     R7, R14, #jit_code_start	;R7=original address
   TEQ     R1, R7
   STRNE   R1, jit_prev_instrL

   #if JIT_debug == 1 AND compile_DEBUG == 1
     TEMP    R1
     STR     R12, DAV_r0 + (12 * 4)	;store R12 as we may overwrite it
     LOCK    R1
     LDR     R0, breakpoint		;report at breakpoint
     TEQ     R14, R0
     ADDEQ   R14, R14, #8
     MOVEQ   R1, #&D			;ADFF500D
     BEQ     JIT_report_unimplemented_debug	;abort
   #endif

   LDR     R0, jit_entry_count		;track how many times we're entered
   ADD     R0, R0, #1
   STR     R0, jit_entry_count
 #endif

 TEMP    R0
 MOV     R1, #0
 STR     R1, JIT_processed_counter	;track number of instr. handled
 #if JIT_predictive_branching == 1
   ADR     R2, JIT_branch_prediction_table
   STR     R1, [R2, #-4]		;reset branch prediction table
 #endif

 #if JIT_cache_consistency == 1
   LDR     R4, JIT_ARM4
   MOV     R7, R14			;preserve R14
   TEQ     R4, #1			;ARMv4 with Cache ON?
   BNE     _skip_consistency_check
   LDR     R4, pre_JIT_wimp_slot_size
   ADD     R4, R4, #jit_code_start
   CMP     R14, R0
   BHI     _check_RMA
   CMP     R14, #jit_code_start
   BLO     _skip_consistency_check
   BL      JIT_ARMv4_consistency
   B       _skip_consistency_check_P1

   ._check_RMA
   BL      JIT_ARMv4_consistency_RMA

   ._skip_consistency_check_P1
   MOV     R14, R7			;preserve R14

   ._skip_consistency_check
 #endif

.JIT_next_instruction_branch_prediction
 STR     R14, JIT_started_at		;track so we can clean the cache
 LOCK    R0

.JIT_next_instruction
 #if compile_DEBUG == 1 AND JIT_debug == 1
   LDR     R0, breakpoint		;report at breakpoint
   TEQ     R14, R0
   BEQ     i_und_exit_hit_limit
 #endif
 #if JIT_instruction_trace == 1
   LDR     R0, instruction_trace_ptr
   LDR     R2, [R0, #-4]
   ORR     R14, R14, #&C << 28
   STR     R14, [R2], #4
   BIC     R14, R14, #&F << 28
   BIC     R2, R2, #jit_trace_buffer_size
   STR     R2, [R0, #-4]
 #endif

 LDR     R2, JIT_processed_counter	;how many instr. we've processed
 LDR     R1, branch_to_jit_no_condition	;JIT entry instruction
 ADD     R2, R2, #1
 CMP     R2, #JIT_max_instructions	;is it time to exit?
 BGT     i_und_exit_hit_limit		;YES
 TEMP    R0
 STR     R2, JIT_processed_counter
 LOCK    R0

 SUB     R7, R14, #jit_code_start	;R7=original address
 LDR     R0, [R14], #8			;get instruction and add prefetch

 #if JIT_debug == 1
   STR     R7, jit_last_instrR
   LDR     R4, jit_instr_count
   ADD     R4, R4, #1
   STR     R4, jit_instr_count
   LDR     R4, jit_instr_interpreted
   ADD     R4, R4, #1
   STR     R4, jit_instr_interpreted
 #endif

 TEQ     R1, R0, LSL #4			;is it a JIT entry?
 BNE     check_copro			;NO, flush cache and retry
					;------------------------------
					;write protect page
 #if JIT_self_modifying_support == 1
   LDR     R4, JIT_ARM4
   TEQ     R4, #1			;ARMv4 with Cache ON?
   BEQ     hv_ARM4_mode			;YES
   CMP     R7, #page_zero_Scratch_Space	;page zero?
   MOVLO   R0, R14			;YES
   BLLO    task_page_zero_R4
   ADDLO   R7, R7, R4
   MOVLO   R14, R0

   LDR     R0, L2PT_addr		;ARM710VE-83 / 85
   LDR     R4, subpages_supported
   ADD     R0, R0, R7, LSR #10		;L2PT entry address for page
   TST     R4, #1			;subpages supported?
   ANDNE   R3, R0, #%11			;YES, R3=1KB sub-page
   MOVNE   R3, R3, LSL #1		; |
   MOVNE   R2, #%01 << 4		; |+  R2=AP mask
   BIC     R0, R0, #%11			;align to word
   LDR     R1, [R0, #0]
   BICNE   R2, R1, R2, LSL R3		;YES, user is read-only
   BICEQ   R2, R1, R4, LSR #16		;NO, user is read-only
   TEQ     R1, R2			;is page already read-only?
   #if JIT_self_modifying_support == 1 AND compile_IOMD == 1
     SWPNE   R2, R2, [R0]		;NO, make read only and flush WB
   #endif
   #if JIT_self_modifying_support == 1 AND compile_IOMD == 0
     STRNE   R2, [R0, #0]		;NO, make read only
   #endif
   #if JIT_self_modifying_support == 1 AND JIT_flush_TLB == 1
     MOV     R1, R14			;preserve R14
     CACHEOP_INVALIDATE_TLB_ENTRYNE R7	;invalidate D TLB entry
     MOV     R14, R1			;preserve R14 / fix for 80321 errata 7
   #endif
   .hv_ARM4_mode
 #endif
					;------------------------------
 LDR     R1, JIT_fixups			;+fix for 80321 errata 7
 #if compile_RO > 400
   MOV     R2, R14			;PMP will corrupt R14
 #endif
 LDR     R0, [R7], #8			;R0=instruction, add prefetch

 #if JIT_detailed_debug == 1
   STR     R0, jit_disassemble_last
   STR     R7, jit_disassemble_last + 4
 #endif
 #if compile_RO > 400
   MOV     R14, R2
 #endif
 #if JIT_self_modifying_support == 1
   SUB     R7, R14, #jit_code_start	;R7=original address
 #endif

 TEQ     R1, #0				;are there any fixups to action?
 BEQ     _no_fixups			;NO, skip

 SUB     R2, R1, #jit_fixup_table.size - 4
 LDR     R1, [R1, #0]			;get fixup count
 TEQ     R1, #0				;are there any fixups to action?
 BEQ     _no_fixups			;NO, skip
 ._fixup_L1
   ADD     R2, R2, #jit_fixup_table.size
   LDR     R3, [R2, #jit_fixup_table.address]
   TST     R3, #jit_fixup_live_flag	;have we dealt with it?
   BEQ     _fixup_L1			;YES

   BIC     R4, R3, #%11			;clear flags
   TEQ     R4, R7			;does this address need replacing?
   LDREQ   R4, [R2, #jit_fixup_table.original] ;YES
   TEQEQ   R4, R0			;does the instruction match?
   BEQ     _fixup_replace		;YES, replace

   SUBS    R1, R1, #1			;any fixups left?
 BNE     _fixup_L1			;YES
 B       _no_fixups			;NO

 ._fixup_replace
 LDR     R0, [R2, #jit_fixup_table.replace] ;YES, replace the instruction
 TST     R3, #jit_fixup_persistent_flag	;is this a persistent replace?
 BICEQ   R3, R3, #jit_fixup_live_flag	;NO, mark as actioned
 STREQ   R3, [R2, #jit_fixup_table.address]
 LDREQ   R3, JIT_fixups
 LDREQ   R1, [R3]
 SUBEQ   R1, R1, #1			;reduce fixup count
 STREQ   R1, [R3]

 ._no_fixups
 AND     R4, R0, #OP_condition
 TEQ     R4, #%1111 << 28		;NV?
 MOVEQ   R0, #%1101 << 21		;YES, replace with NOP
 BEQ     i_copy_instruction_handled

 #if JIT_debug == 1 AND JIT_report_zeros == 1
   TEQ     R0, #0			;0 usually indicates an illegal
   MOVEQ   R1, #&13			;ADFF5013
   BEQ     JIT_report_unimplemented	;branch, or badly written software
 					;in the case of MiG-29
 #endif

 AND     R1, R0, #%1111 << 24
 ADD     PC, PC, R1, LSR #24 - 2
 NOP
 B       i_ALU				;0000 ALU / MUL
 B       i_ALU				;0001 ALU / SWP
 B       i_ALU				;0010 ALU
 B       i_ALU				;0011 ALU
 B       i_LDR_STR			;0100 LDR / STR
 B       i_LDR_STR			;0101 LDR / STR
 B       i_LDR_STR			;0110 LDR / STR / Undefined
 B       i_LDR_STR			;0111 LDR / STR / Undefined
 B       i_LDM_STM			;1000 LDM / STM
 B       i_LDM_STM			;1001 LDM / STM
 B       i_B				;1010 B
 B       i_BL				;1011 BL
 B       i_LDF_STF_post_indexed		;1100 Co-pro data transfer
 B       i_LDF_STF			;1101 Co-pro data transfer
 B       i_copro			;1110 Co-pro
 B       i_SWI				;1111 SWI




.check_copro
 #if JIT_debug == 1
   LDR     R4, jit_instr_count
   SUB     R4, R4, #1
   STR     R4, jit_instr_count
   LDR     R4, jit_instr_interpreted
   SUB     R4, R4, #1
   STR     R4, jit_instr_interpreted
 #endif

 AND     R4, R0, #%1111 << 24		;is it a Co-pro instruction?
 TEQ     R4, #%1100 << 24
 TEQNE   R4, #%1101 << 24
 TEQNE   R4, #%1110 << 24
 DID_JIT_ENTER_HEREEQ			;YES, did the JIT enter here?
 BEQ     pass_to_previous_Und		; |+  YES, pass to RISCOS
B       i_und_exit_no_codelet		;NO, continue at branch prediction




.i_instruction_handled
 CACHEOP_CLEAN_CODELET

.i_instruction_handled_no_codelet
 SUB     R14, R14, #4			;go to next instruction
B       JIT_next_instruction




.i_copy_instruction
 #if JIT_debug == 1
   LDR     R4, jit_instr_interpreted
   SUB     R4, R4, #1
   STR     R4, jit_instr_interpreted
 #endif
;fall-thru to i_copy_instruction_handled

;i_copy_instruction_handled
;--------------------------
;Write instruction contained in R0 to JIT appspace and then continue
;processing instructions

.i_copy_instruction_handled
 STR     R0, [R14, #-8]			;copy instruction

 SUB     R14, R14, #4			;go to next instruction
B       JIT_next_instruction




;i_copy_and_exit
;---------------
;Write instruction contained in R0 to JIT appspace and then exit JIT

.i_copy_and_exit
 #if JIT_debug == 1
   LDR     R4, jit_instr_interpreted
   SUB     R4, R4, #1
   STR     R4, jit_instr_interpreted
 #endif
;fall-thru to i_copy_and_exit_handled


;i_copy_and_exit_handled
;-----------------------
;Write instruction contained in R0 to JIT appspace and then exit JIT

.i_copy_and_exit_handled
 STR     R0, [R14, #-8]			;copy instruction
B       i_und_exit_no_codelet




;JIT_branch_prediction
;---------------------
;follow predicted branch
;
;Entry:
; R1 - updated BPT index to write back
; R6 - address to follow

#if JIT_predictive_branching == 1
.JIT_branch_prediction
 STR     R1, [R7, #-4]			;update BPT index

 CACHEOP_CLEAN_APPSPACE_TO_HERE		;clean appspace to here
 MOV     R14, R6			;and start processing

B       JIT_next_instruction_branch_prediction
#endif



;i_und_exit
;----------
;Exit JIT cleaning a codelet that's just been written

.i_und_exit
 CACHEOP_CLEAN_CODELET			;clean last codelet from D cache

;fall-thru to i_und_exit_no_codelet


;i_und_exit_no_codelet
;---------------------
;Exit JIT, no codelet to clean

.i_und_exit_no_codelet
					;---------------------------------
					;BRANCH PREDICTION
					;---------------------------------
#if JIT_predictive_branching == 1
 ADR     R7, JIT_branch_prediction_table
 LDR     R1, [R7, #-4]			;get current index pointer
 LDR     R4, branch_to_jit_no_condition	;JIT entry instruction
 ._L1
   SUBS    R1, R1, #1			;last BPT entry?
   BMI     i_und_exit_hit_limit		;YES

   LDR     R6, [R7, R1, LSL #2]		;get address to predict
   LDR     R3, [R6]			;get the instruction at the Branch
   TEQ     R4, R3, LSL #4		;is it a JIT entry?
   BEQ     JIT_branch_prediction	;YES, follow it
 B       _L1				;NO, go to next BPT entry
#endif
					;----------------------------------


;i_und_exit_hit_limit
;---------------------
;Exit JIT immediately, we've processed the instruction limit

.i_und_exit_hit_limit
 CACHEOP_CLEAN_APPSPACE_TO_HERE		;clean D cache up to here
 BL      CACHEOP_ACTION			;act on pending cache ops

 #if JIT_report_immediate == 1
   LDR     R0, [R13, #8 * 4]
   SUB     R0, R0, #jit_code_start
   STR     R0, user_PC

   #if JIT_report_immediate == 1 AND JIT_report_registers == 1
;STACK: R0-R7,R14
     ADR     R14, DAV_r0
     LDMIA   R13, {R0-R7}
     STMIA   R14!, {R0-R12}
     LDR     R0, [R13, #8 * 4]
     STR     R0, [R14, #2 * 4]		;..fix for errata on SA-110 rev.2
     STMIA   R14, {R13, R14}^
     NOP
   #endif
   BL      report_JIT			;display JIT information
 #endif
LDMFD   R13!, {R0-R7, PC}^		;retry instruction




.i_LDR_STR
 TST     R0, #1 << 25			;Undefined?
 TSTNE   R0, #1 << 4
 MOVNE   R1, #9				;ADFF5009
 BNE     JIT_report_unimplemented	;YET TO BE CODED

 TST     R0, #1 << 25			;is Op2 a register?
 MVNEQ   R3, #0				;NO, R3=<bad value> for checks later
 BEQ     _immediate			; |+ skip Rm PC check

 AND     R3, R0, #%1111			;R3=Rm
 TEQ     R3, #PC_reg			;is PC in Rm? ie: STR R0,[R1,PC]
 MOVEQ   R1, #9				;ADFF5009
 BEQ     JIT_report_unimplemented	;YET TO BE CODED
 ._immediate

 AND     R1, R0, #%1111 << 12		;R1=Rd
 AND     R2, R0, #%1111 << 16		;R2=Rn

 TST     R0, #1 << 20			;LDR?
 BEQ     i_STR				;NO

#if High_Vectors == 1
 B       i_LDR
#endif
#if High_Vectors == 0
					;check for page zero reads
					;----------------------------------
;EXCLUDE:	LDR PC,...
 TEQ     R1, #PC_reg << 12		;:LDR PC, ...?
 BEQ     i_LDR_PC_in_Rd			;YES

;EXCLUDE:	LDR Rd,[PC, #<immed>]
;EXCLUDE:	LDR Rd,[PC],#<immed>
 TEQ     R2, #PC_reg << 16		;:LDR Rx, [PC, ... ?
 TSTEQ   R0, #1 << 25			;YES, is Op2 an immediate?
 BEQ     i_LDR				;YES

 DID_JIT_ENTER_HERE			;did the JIT entered here?
 BEQ     LDR_check			;YES

 LDR     R1, [R7, #-8]			;NO, get the original instruction
 TEQ     R1, R0				;has it changed?
 LDREQ   R2, branch_to_jit_no_condition	;NO, JIT entry instruction
 ANDEQ   R1, R1, #OP_condition		; |  get instruction condition
 ORREQ   R0, R1, R2, LSR #4		; |+ add conditional JIT entry
					;YES, trust the code is okay
B       i_copy_instruction_handled	;continue processing
#endif




.i_LDM_STM
#if JIT_cache_consistency == 0
 LDR     R1, _LDMIA_R13_PC		;: LDMIA R13!,{PC}?
 TEQ     R0, R1
 LDREQ   R0, _LDR_PC_R13_4		;YES, change to: LDR PC,[R13],#4
 BEQ     i_LDR_STR

 LDR     R1, _STMDB_R13_R14		;: STMDB R13!,{R14}?
 TEQ     R0, R1
 LDREQ   R0, _STR_R14_R13_4		;YES, change to: STR R14,[R13,#-4]!
 BEQ     i_copy_instruction
#endif

 ORR     R1, R0, R0, LSL #16
 CMN     R1, #1				;: LDM/STM Rd{!},{R0-PC}{^} ?
 MOVEQ   R1, #9				;YES, ADFF5009
 BEQ     JIT_report_unimplemented

 AND     R1, R0, #%1111 << 16		;R1=Rn
 TEQ     R1, #PC_reg << 16		;is Rn PC? : LDM/STM PC{!}, ...
 BEQ     _i_LDM_STM_PC_in_Rn		;YES
					;----------------------------------
					;change: LDMIA R0!,{R0}
					;    to: LDMIA R0,{R0}
 MOV     R4, R1, LSR #16		;R4=Rn
 MOV     R2, #1
 TST     R0, R2, LSL R4			;is Rn in the reglist?
 BEQ     _Rn_not_in_reglist		;NO

 TST     R0, #1 << 20			;YES, LDM?
 BICNE   R0, R0, #1 << 21		; |+  YES, clear writeback
 #if ARMv7_support == 1
   BNE     _Rn_not_in_reglist
   TST     R0, #1 << 21			;STM, writeback?
   BNE     i_STM_Rn_in_reglist		;YES
 #endif
 ._Rn_not_in_reglist
					;----------------------------------
; #if ARMv7_support == 1
;   TST     R0, #1 << 13			;is R13 in reg_list?
;   MOVNE   R1, #&17
;   BNE     JIT_report_unimplemented	;YES, ADFF5017
; #endif

 TST     R0, #PC_reglist		;:LDM/STM Rn{!}, {<reg_list>, PC}?
; #if ARMv7_support == 1
;   BICEQ   R0, R0, #1 << 22		;NO, ensure ^ isn't set
;					;(fixes Zarch/Chopper Force on ARMv7)
; #endif
 BEQ     i_copy_instruction

 TST     R0, #1 << 20			;LDM?
 BNE     i_LDM				;YES
B       i_STM

#if JIT_cache_consistency == 0
 ._LDMIA_R13_PC		LDMIA   R13!, {PC}
 ._LDR_PC_R13_4		LDR     PC, [R13], #4
 ._STMDB_R13_R14	STMDB   R13!, {R14}
 ._STR_R14_R13_4	STR     R14, [R13, #-4]!
#endif


._i_LDM_STM_PC_in_Rn
 TST     R0, #PC_reglist		;is PC in the reglist?
 MOVNE   R1, #9				;YES, ADFF5009
 BNE     JIT_report_unimplemented	;unsupported

 BIC     R0, R0, #1 << 21		;clear writeback

 TST     R0, #1 << 20			;LDM?
 BEQ     i_STM_PC_in_Rn
B       i_LDM_PC_in_Rn




;JIT_report_illegal
;------------------
;report an illegal branch address

.JIT_report_illegal_address
 ADD     R14, R14, #8
 MOV     R1, #&13			;ADFF5013
B       JIT_report_unimplemented_debug



;JIT_report_unimplemented
;------------------------
;report an unimplemented feature
;
;Entry:
; R1 - ADFFS error number (see data_abort.report_abort)

.JIT_report_unimplemented
 DID_JIT_ENTER_HERE			;did the JIT enter on this instr?
 BNE     i_und_exit_no_codelet		;NO, assume it's going to self-
					;    modify and check branch pred.
.JIT_report_unimplemented_debug
 TEMP    R2
 ADD     R12, R1, #&ADFF5000
 STR     R12, current_abort_type
 LDR     R12, DAV_r0 + (12 * 4)
 LOCK    R2

 ADR     R0, DAV_r0
 SUB     R1, R14, #8
 SUB     R1, R1, #jit_code_start
 STR     R1, [R0, #15 * 4]		;store PC

 LDR     R1, [R13], #4			;pull R0 from stack
 STR     R1, [R0], #4
 LDMFD   R13!, {R1-R7, R14}		;restore registers
 STMIA   R0!, {R1-R7}			;store unbanked registers

 MRS     R1, SPSR			;get original CPU state
 TST     R1, #%1111			;is abort in User mode?
 TEMP    R2
 STR     R1, DAV_CPSR			;store it for exit and..
 LOCK    R2				;..fix for errata on SA-110 rev.2
 STMEQIA R0, {R8-R14}^			;get User mode registers
 BEQ     _P2

 MRS     R2, CPSR
 MSR     CPSR_c, R1			;switch to faulting mode
 #if compile_IOMD == 1
   NOP
 #endif
 STMIA   R0, {R8-R14}			;get aborting mode registers
 MSR     CPSR_c, R2
 #if compile_IOMD == 1
   NOP
 #endif

 ._P2
 #if JIT_debug == 1 AND JIT_dump_crash == 1
   ADR     R1, breakpoint_dump
   MOV     R4, #&8000
   MOV     R2, R4
   MOV     R3, #0
   MOV     R5, #jit_slotsize

   MRS     R7, CPSR
   BIC     R0, R7, #%11001111		;retain reserved bit
   ORR     R0, R0, #%00000011		;SVC with IRQ/FIQ enabled
   MSR     CPSR_all, R0
   NOP
   MOV     R0, #0
   SWI     XOS_File
   MSR     CPSR_all, R7
   NOP
 #endif
B       report_abort
