;blank line to work around bug in extASM (if on 1st line is ignored)
#if compile_RO == 400
  #set jit_allocate_memory	= &A00000	;total memory for JIT
  #set jit_RMA_size		= &180000	;total memory for JIT RMA
  #set jit_slotsize		= &1880000	;ram to allocate for appspace
  #set jit_code_start		= jit_slotsize - (jit_allocate_memory + jit_RMA_size)
				;D00000
  #set jit_ram			= jit_slotsize	;highest address for WimpSlot
#endif
#if compile_RO > 400
  #set jit_allocate_memory	= &D00000	;total memory for JIT
  #set jit_RMA_size		= &100000	;total memory for JIT RMA
  #set jit_slotsize		= &1F00000	;ram to allocate for appspace
  #set jit_code_start		= jit_slotsize - (jit_allocate_memory + jit_RMA_size)
				;1100000
  #set jit_ram			= &1F08000	;highest address for WimpSlot
						;includes pointer/sound buffers
#endif
#if compile_RO == 450
  #set jit_ram			= &1F18000	;highest address for WimpSlot
#endif

#set jit_appspace_end	= jit_allocate_memory + jit_RMA_size
						;max RAM JIT supports
						;16mb is theorical max
#set jit_RMA_heap	= jit_allocate_memory	;start of JIT RMA

#set jit_page_zero	= jit_code_start - page_zero_Scratch_Space

#set lastfree_codelet	= jit_appspace_end	;last free block in codelets

#set jit_trace_buffer_size	= &400000	;size of the trace buffer
						;length must have only 1 bit set
						;for the overrun code to work

#set jit_26bit_exits = jit_code_start+jit_RMA_heap+jit_RMA_size
#set jit_26bit_exit_size = 64

.Entry_GOARM3JIT
 STMFD   R13!, {R12, R14}
 LDR     R12, [R12, #0]

 TEQ     R1, #0				;are we shutting down?
 BEQ     Entry_GOARMxJIT		;YES

 LDR     R14, [R12, #jit_code - VARS]
 TEQ     R14, #0			;is the JIT running?
 LDRNEB  R14, [R12, #JIT_ARM4 - VARS]	;YES, is it in ARMv3 mode?
 TEQNE   R14, #0
					;EQ if YES, notify JIT to startup in ARMv3 mode
.Entry_GOARM3JIT_P1
 STREQ   R14, [R12, #JIT_ARM4 - VARS]
 BEQ     Entry_GOARMxJIT		;..with the cache enabled

 MOV     R0, #1 << 31			;NO, running in ARMv4, report an error
 ADDS    R0, R0, R0			;set V
 ADR     R0, Error_JIT_ARM3_or_4	;report error
LDMFD   R13!, {R12, PC}



;Entry:
; R12 - pointer to VARS
; {R12, R14} - stacked

.Entry_GOARMxJIT
 TEQ     R1, #0				;are we initialising?
 MOV     R1, R0
 STMFD   R13!, {R1-R11}
 BNE     _P1				;YES

 LDR     R0, [R12, #jit_code - VARS]	;NO, shutting down
 TEQ     R0, #0				;is the JIT running?
 LDMEQFD R13!, {R1-R12, PC}		;NO, exit

 BL      shutdown_interrupts
 BL      kill_26bit_modules		;kill legacy modules
 BL      remove_this_taskID		;remove this taskID
 LDR     R0, [R12, #jit_task_count - VARS]
 TEQ     R0, #0				;is this the last task
 BNE     _not_last_task			;NO

 MOV     R0, #&8000
 MOV     R1, #&10000
 SWI     XOS_DelinkApplication		;ensure we have definitely removed all vectors

 BL      _set_ADFFS_JIT
 #if Managed_ChannelHandler == 1
   BL      reset_sound_configure	;reset audio subsystem
 #endif
 BL      clear_jitmemorya		;remove any buffered code changes

 BL      _release_processor_vectors
 LDMVSFD R13!, {R1-R12, PC}

 LDRB    R0, [R12, #BASICTrans_loaded - VARS]
 TEQ     R0, #0
 MOVNE   R0, #Module_Delete		;RMKill BASIC module
 ADRNE   R1, _BASICTrans
 SWINE   XOS_Module			;PRM1-235
 MOV     R0, #0
 STRB    R0, [R12, #BASICTrans_loaded - VARS]

 BL      Remove_Transient_DA

 MOV     R0, #0
 STR     R0, [R12, #jit_code - VARS]
 STR     R0, [R12, #JIT_event11_active - VARS]		;reset Event 11 counter

 #if JIT_protect_page_zero == 1
   LDR     R0, [R12, #os_version - VARS]	;ARM710VE-83 / 85
   CMP     R0, #&380 << 8			;are we below RO3.8?
   LDRLO   R1, [R12, #page_zero_L2PT - VARS]	;YES, restore page zero protection
   MOVLO   R0, #0				; |
   BLLO    MMUControl_ARMop5_SA			; |+ invalidate TLB entry
 #endif

 #if Unaligned_Support == 1 OR compile_RO == 500
   MOV     R1, #0
   LDR     R0, [R12, #Current_Machine_State - VARS + Machine_State.cpu_control_register]
   TEQ     R0, #0			;did we change the CPU CR?
   STRNE   R1, [R12, #Current_Machine_State - VARS + Machine_State.cpu_control_register]
   MCRNE   P15, 0, R0, C1, C0, 0	;YES, set it back
 #endif

 #if High_Vectors == 1
 ;ref. https://www.riscosopen.org/wiki/documentation/show/OS_Memory%2020
   MOV     R0, #20			;check compatibility page
   MVN     R1, #0
   SWI     XOS_Memory
   LDR     R2, [R12, #Current_Machine_State - VARS + Machine_State.OS_Memory20]
   TEQ     R1, R2			;did we change it?
   MOVNE   R1, R2			;YES
   SWINE   XOS_Memory
 #endif

 MVN     R0, #0				;reset RISCOS emulation
 STR     R0, [R12, #emulate_RISCOS - VARS]

 ._not_last_task
 #if JIT_self_modifying_support == 1
   BL      reset_appspace_L2PT
 #endif

 MOV     R0, #WimpSysInfo_CurrentTaskHandle	;get task handle
 SWI     XWimp_ReadSysInfo		;PRM3-216
 TEQ     R0, #0				;do we need to remove Filters
 BLNE    Remove_Wimp_Filters		;YES

 SUBS    R0, R0, R0			;clear V
LDMFD   R13!, {R1-R12, PC}

 ._VProtect DCB "VProtect", 0
 ALIGN

 ._P1
 LDRB    R0, [R12, #JIT_ARM4 - VARS]
 TEQ     R0, #0
 LDR     R0, [R12, #emulate_RISCOS - VARS]
 BEQ     _armv3
 CMP     R0, #&370 << 8
 MOVLT   R0, #&371 << 8			;ensure we're emulating at least RO3.71 for ARMv4
 STRLT   R0, [R12, #emulate_RISCOS - VARS]
 ._armv3

 MOV     R0, #Module_Lookup
 ADR     R1, _VProtect
 SWI     XOS_Module			;check for VProtect
 TEQ     R0, #Module_Lookup		;is VProtect running?
 MOVNE   R3, #0				;NO
 MOVNE   R1, #0
 LDREQ   R1, [R3, #-4]			;YES, get size of VProtect Module
 STR     R3, [R12, #VProtect_Module - VARS]
 STR     R1, [R12, #VProtect_Module + 4 - VARS]

 #if JIT_debug == 1 AND compile_IOMD == 1
   BL      get_screen_start
   MOV     R0, #dbg_pause_default
   TEMP    R1
   STR     R0, dbg_pause
   LOCK    R1
 #endif

 LDR     R0, [R12, #jit_code - VARS]
 TEQ     R0, #0				;is the JIT already setup?
 BNE     _already_setup			; |+ skip initialisation

 #if use_overlay == 1 AND JIT_debug == 1
   BL      create_debug_overlay
   BL      display_debug_overlay
 #endif

 BL      store_machine_state		;store key repeat etc

 #if compile_RO == 400
   MVN     R0, #0			;read current slotsize
   MVN     R1, #0
   SWI     XWimp_SlotSize		;PRM3-203
  
   MOV     R1, #jit_allocate_memory - &8000	;RAM limit
   CMP     R0, R1			;do we have enough RAM?
   MOVHS   R3, R1			;cap at jit_ram limit
   MOVLO   R3, R0			;store current slotsize
   MOV     R1, #jit_ram - &8000
   CMP     R0, R1			;do we have enough RAM?
   MOVLO   R0, R1			;NO, allocate more
   MVNLO   R1, #0
   SWILO   XWimp_SlotSize		;PRM3-203
   LDMVSFD R13!, {R1-R12, PC}		;exit on error
  
   MVN     R0, #0			;read current slotsize
   MVN     R1, #0
   SWI     XWimp_SlotSize		;PRM3-203
   MOV     R1, #jit_ram - &8000
   CMP     R0, R1			;do we have enough RAM?
   MOVLO   R0, #1 << 31			;NO, set V
   ADDLOS  R0, R0, R0
   ADRVS   R0, Error_jit_slotsize
   LDMVSFD R13!, {R1-R12, PC}		;exit on error
   STR     R3, [R12, #pre_JIT_wimp_slot_size - VARS]	;store current WimpSlot
 #endif
 #if compile_RO >= 450
   MOV     R0, #15			;read current slotsize
   SWI     XWimp_Extend			;RO 5.27+
   TEQ     R0, #15			;did it work?
   LDRNE   R4, [R12, #current_PageSizeSH - VARS]	;YES
   MOVEQ   R4, #0			;NO
   MVNEQ   R0, #0			;read current slotsize
   MVNEQ   R1, #0
   SWIEQ   XWimp_SlotSize		;PRM3-203

   MOV     R1, #jit_allocate_memory - &8000	;RAM limit
   CMP     R0, R1, LSR R4		;do we have enough RAM?
   MOVHS   R3, R1			;cap at jit_ram limit
   MOVLO   R3, R0, LSL R4		;store current slotsize
   MOVLO   R0, #jit_ram - &8000		;NO, allocate more
   MVNLO   R1, #0
   SWILO   XWimp_SlotSize		;PRM3-203
   LDMVSFD R13!, {R1-R12, PC}		;exit on error
  
   MOV     R0, #15			;read current slotsize
   SWI     XWimp_Extend			;PRM3-203
   TEQ     R0, #15			;did it work?
   MVNEQ   R0, #0			;read current slotsize
   MVNEQ   R1, #0
   SWIEQ   XWimp_SlotSize		;PRM3-203

   MOV     R1, #jit_ram - &8000
   CMP     R0, R1, LSR R4		;do we have enough RAM?
   MOVLO   R0, #1 << 31			;NO, set V
   ADDLOS  R0, R0, R0
   ADRVS   R0, Error_jit_slotsize
   LDMVSFD R13!, {R1-R12, PC}		;exit on error
   STR     R3, [R12, #pre_JIT_wimp_slot_size - VARS]	;store current WimpSlot
 #endif

 MOV     R0, #Heap_Initialise		;initialise JIT RMA heap
 MOV     R1, #jit_RMA_heap
 MOV     R3, #jit_RMA_size-jit_26bit_exit_size
 SWI     XOS_Heap			;PRM1-377

 ADD     R7, R12, #MEMC_registers - VARS	;reset MEMC registers
 MOV     R0, #RO3xx_Pointer_Buffer
 STR     R0, [R7, #IOC_Cinit << 2]	;Pointer
 LDR     R0, _default_MEMC_CR
 STR     R0, [R7, #MEMC_CR << 2]

 MOV     R0, #0
 #if compile_RO > 400
   BL      reset_IOC
 #endif

 TEMP    R1
 STR     R0, linear_handler_entry	;reset sound handler
 STR     R0, [R12, #Module_being_inserted - VARS]	;reset
 LOCK    R1

 ADD     R0, R12, #DeviceVectors - VARS	;initialise Device Vector claims
 ADD     R1, R0, #(last_device_to_track + 1) * device_table.size
 BL      ZeroBlock

 ADR     R2, Current_Machine_State
 #if compile_RO == 500
   MRC     P15, 0, R0, C1, C0, 0	;get CPU control register
					;see ARM ARM rev.I B3-12
   BIC     R3, R0, #1 << 1		;disable alignment fault checking
   BIC     R3, R3, #1 << 22		;enable rotated unaligned loads
   TEQ     R0, R3
   STRNE   R0, [R2, #Machine_State.cpu_control_register]
   MCRNE   P15, 0, R3, C1, C0, 0	;update ARM Control Register
 #endif
 #if Unaligned_Support == 1
   MRC     P15, 0, R0, C1, C0, 0	;get CPU control register
					;see ARM ARM rev.I B3-12
   ORR     R3, R0, #1 << 1		;enable alignment fault checking
   TEQ     R0, R3
   STRNE   R0, [R2, #Machine_State.cpu_control_register]
   MCRNE   P15, 0, R3, C1, C0, 0	;update ARM Control Register
 #endif

 #if High_Vectors == 1
;ref. https://www.riscosopen.org/wiki/documentation/show/OS_Memory%2020
   MOV     R0, #20			;check compatibility page
   MVN     R1, #0
   SWI     XOS_Memory
   MVNVS   R1, #0
   STR     R1, [R2, #Machine_State.OS_Memory20]
   TEQ     R1, #1			;is page zero mapped?
   MOVEQ   R1, #0			;YES
   SWIEQ   XOS_Memory			; |+ disable page
 #endif

 #if JIT_protect_page_zero == 1
   LDR     R0, [R12, #os_version - VARS]	;ARM710VE-83 / 85
   CMP     R0, #&380 << 8		;are we below RO3.8?
   TEMP    R3
   LDRLO   R0, L2PT_addr		;YES, protect page zero
   LOCK    R3
   LDRLO   R1, [R0, #0]			; |  page zero L2PT
   STRLO   R1, [R12, #page_zero_L2PT - VARS]		; |  keep a copy for later
   BICLO   R1, R1, #%11111111 << 4	; |  user is read-only
   ORRLO   R1, R1, #%11101010 << 4	; |  protect 0..&2FFF
   STRLO   R1, [R0, #0]			; |  update TLB
   MOVLO   R0, #0			; |
   BLLO    MMUControl_ARMop5_SA		; |+ Invalidate TLB entry
 #endif
					;Now setup the JIT space ready for
					;translated code
 BL      task_page_zero_R0
 MOV     R3, #jit_code_start
 MOV     R9, #0
 MOV     R10, #0
 MOV     R11, #0
 MOV     R14, #0
 ADD     R8, R3, #page_zero_Scratch_Space	;clear page zero
 ._PZ_L1
   STMIA    R0!, {R9-R11, R14}
   STMIA    R0!, {R9-R11, R14}
   TEQ      R0, R8
 BNE     _PZ_L1

 LDR     R1, branch_to_jit		;instruction to enter JIT
 MOV     R2, R1, LSL #4
 TEMP    R7
 STR     R2, branch_to_jit_no_condition	;used to quickly check for Hypercalls
 LOCK    R7
 MOV     R2, R1
 MOV     R4, R1
 MOV     R5, R1
 MOV     R6, R1
 MOV     R7, R1
 MOV     R8, R1
 MOV     R0, R1

 MOV     R3, #jit_code_start
 ._L2
   STMIA   R3!, {R0-R2, R4-R8}
   STMIA   R3!, {R0-R2, R4-R8}
   STMIA   R3!, {R0-R2, R4-R8}
   STMIA   R3!, {R0-R2, R4-R8}
   TEQ     R3, #jit_slotsize
 BNE     _L2

 #if JIT_trap_pz_code == 1
   LDR     R4, JIT_pz_code		;trap branching into page zero
   MOV     R5, R4
   MOV     R6, R4
   MOV     R7, R4
   MOV     R3, #jit_code_start
   ADD     R8, R3, #page_zero_Scratch_Space
   ._PZ_L2
     STMIA    R3!, {R4-R7}
     STMIA    R3!, {R4-R7}
     TEQ      R3, R8
   BNE     _PZ_L2
 #endif

 #if compile_DEBUG == 1 OR JIT_instruction_trace == 1	;force chocolate off
   MOV     R0, #5			;turn lazy page mapping off
   MOV     R1, #0
   SWI     XOS_AMBControl

   MOV     R3, #page_zero_Scratch_Space
   LDR     R4, [R12, #current_PageSize - VARS]
   ._L1_chocolate
     LDR     R0, [R3], R4		;force pages to be mapped
     CMP     R3, #jit_code_start
   BLO     _L1_chocolate
 #endif

 BL      Create_Transient_DA		;create transient DA's
 #if JIT_instruction_trace == 1
   LDR     R3, [R12, #instruction_trace_ptr - VARS]
   STR     R3, [R3, #-4]		;reset the instruction trace ptr
 #endif

 SWI     XOS_GetEnv				;get EnvString
 STR     R0, [R12, #page_zero_EnvString - VARS]	;used in page_zero_abort handler
 STR     R2, [R12, #page_zero_EnvTime - VARS]	;used in page_zero_abort handler

 MOV     R0, #0					;reset hypervised IRQ handlers
 STR     R0, [R12, #transient_stacks_used - VARS]
 TEMP    R3
 STR     R0, terminate_all_voices
 #if JIT_debug == 1
   STR     R0, jit_codelet_count
   STR     R0, jit_joysticks
 #endif
 LOCK    R3
					;setup exit code below 27.5mb
 MOV     R0, #jit_26bit_exits
 LDR     R1, _codelet_os_exit		;OS_Exit for general use
 STR     R1, [R0, #-4]!
 SUB     R1, R0, #jit_code_start
 STR     R1, [R12, #jit_managed_os_exit - VARS]

 ADR     R5, _codelet1			;SWI 0 for general use
 LDMIA   R5, {R1-R2}
 STMDB   R0!, {R1-R3}			;entry for us
 STR     R0, [R12, #jit_managed_swi - VARS]

 ADR     R5, _codelet2			;LDR PC, [R13], #4 for general use
 LDMIA   R5, {R1-R3}
 STMDB   R0!, {R1-R3}			;entry for us
 ADD     R1, R0, #8			;skip the two NOP's
 SUB     R1, R1, #jit_code_start
 STR     R1, [R12, #jit_managed_ldr_pc_r13 - VARS]
 
 ADR     R5, _codelet3			;LDR PC, [R13+4], #4 for general use
 LDMIA   R5, {R1-R4}
 STMDB   R0!, {R1-R4}			;entry for us
 ADD     R1, R0, #8			;skip the two NOP's
 SUB     R1, R1, #jit_code_start
 BL      task_page_zero_R2
 STR     R1, [R12, #jit_managed_ldr_pc_r13_2 - VARS]	;first code in Appspace
 STR     R1, [R12, #hypervised_IRQ1V - VARS]
 STR     R1, [R2, #page_zero_IRQ1V]

 BL      task_page_zero_R0
 MOV     R6, R0
 SUB     R0, R0, #EnvHandler.size * 17	;space to track environment handlers
 STR     R0, [R12, #environment_handlers - VARS]
 BL      claim_ChangeEnvironmentV	;ensure we've claimed environment handlers
 BL      initialise_vector_table
 BL      get_DA2_size

 MOV     R1, #0
 STR     R1, [R6, #page_zero_CLibCounter]
 STR     R1, [R6, #page_zero_RISCOSLibWord]
 STR     R1, [R6, #page_zero_CLibWord]
					;-----------------------
 SUB     R0, R0, #codelet_struct.codelet	;initialize first codelet
 BIC     R0, R0, #codelet_alignment - 1		;align it
 STR     R0, [R0, #codelet_struct.next]		;next=pointer to itself
 STR     R0, [R0, #codelet_struct.previous]	;previous=pointer to itself
 MOV     R1, #codelet_struct.codelet
 STR     R1, [R0, #codelet_struct.size]		;size=codelet_struct size
 MVN     R1, #0
 STR     R1, [R0, #codelet_struct.source]	;source=-1
 STR     R0, [R12, #first_codelet - VARS]
						;initialize last free codelet
 MOV     R2, #lastfree_codelet			;R2=codelet
 STR     R2, [R2, #codelet_struct.next]		;next=pointer to itself
 STR     R2, [R2, #codelet_struct.previous]	;previous=pointer to itself
 MOV     R1, #0
 STR     R1, [R2, #codelet_struct.source]	;source=0
 SUB     R1, R0, R2				;R1=size
 STR     R1, [R2, #codelet_struct.size]		;size=free space
					;-----------------------
 MOV     R0, #jit_code_start
 STR     R0, [R12, #jit_code - VARS]	;start of translated code

 BL      _claim_processor_vectors	;claim processor vectors
 BVC     _already_setup

 MOV     R1, R0
 BL      _release_processor_vectors
 MOV     R0, R1
 MSR     CPSR_f, #1 << 28		;set V
 LDMFD   R13!, {R1-R12, PC}		;exit

 ._already_setup
 BL      get_taskID			;get current task
 BL      load_softFont			;put softFont into our Page Zero
 BL      init_hardware_vectors		;setup hardware vectors

 ADR     R0, MMUControl_ARMop7
 MOV     R14, PC
 LDR     PC, [R0, #0]			;IMB full

 BL      _unset_ADFFS_JIT		;set environment variable for JIT

 LDR     R1, [R13, #0]			;command tail
 MOV     R0, #16			;base 16 number with restricted range
 SWI     XOS_ReadUnsigned		;read the value PRM1-460
 LDMVSFD R13!, {R1-R12, PC}		;exit on error

 TEQ     R2, #0				;are we simply setting up the JIT?
 LDMEQFD R13!, {R1-R12, PC}		;YES, exit
B       Entry_ADFGO_GOARM3JIT




._claim_processor_vectors
 STR     R14, [R13, #-4]!

 TEMP    R14
 BL      Claim_DataAbort_Vector			;claim DataAbort vector
 LDRVS   PC, [R13], #4

 BL      Claim_Undefined_Vector
 LDRVS   PC, [R13], #4

 MOV     R0, #Vector_IRQ + (1<<8)		;claim IRQ vector
 LDR     R1, existing_IRQVector
 TEQ     R1, #0					;already claimed
 ADREQ   R1, IRQ_Vector_Handler
 SWIEQ   XOS_ClaimProcessorVector		;PRM5a-30
 LDRVS   PC, [R13], #4
 STR     R1, existing_IRQVector			;store existing

 MOV     R0, #Vector_BranchThruZero + (1<<8)	;claim Reset vector
 LDR     R1, [R12, #existing_Branch_thru_zero - VARS]
 TEQ     R1, #0					;already claimed
 ADREQ   R1, Branch_thru_zero
 SWIEQ   XOS_ClaimProcessorVector		;PRM5a-30
 LDRVS   PC, [R13], #4
 STR     R1, [R12, #existing_Branch_thru_zero - VARS]	;store existing

 #if compile_RO > 400
   MOV     R0, #Vector_SeriousErrorV		;claim SeriousError vector
   ADR     R1, seriousErrorV_handler
   MOV     R2, R12				;R2=pointer to VARS
   SWI     XOS_Claim
 #endif

 LOCK    R14
LDR     PC, [R13], #4



._release_processor_vectors
 STMFD   R13!, {R1-R4, R14}

 TEMP    R14
 SUBS    R4, R4, R4			;R4=0 and V clear
 LDRB    R0, [R12, #remapping_video_memory - VARS]
 TEQ     R0, #0				;are we remapping video memory
 BLEQ    release_DataAbort_Vector	;NO, we can shutdown the Abort handler
 MOVVS   R4, R0

 MOV     R3, #0

 SUBS    R2, R2, R2			;V clear
 MOV     R0, #Vector_IRQ		;release IRQ vector
 LDR     R1, existing_IRQVector
 ADR     R2, IRQ_Vector_Handler
 TEQ     R1, #0
 SWINE   XOS_ClaimProcessorVector	;PRM5a-30
 MOVVS   R4, R0
 STRVC   R3, existing_IRQVector

 SUBS    R2, R2, R2			;V clear
 MOV     R0, #Vector_BranchThruZero	;release branch through zero handler
 LDR     R1, existing_Branch_thru_zero
 ADR     R2, Branch_thru_zero
 TEQ     R1, #0
 SWINE   XOS_ClaimProcessorVector	;PRM5a-30
 MOVVS   R4, R0
 STRVC   R3, [R12, #existing_Branch_thru_zero - VARS]

 SUBS    R2, R2, R2			;V clear
 MOV     R0, #Vector_UndefinedInstr	;release Undefined Instruction vector
 LDR     R1, existing_UndefinedInstr
 ADR     R2, Undefined_Instruction_Vector
 TEQ     R1, #0
 SWINE   XOS_ClaimProcessorVector	;PRM5a-30
 MOVVS   R4, R0
 STRVC   R3, existing_UndefinedInstr
 #if compile_RO > 400
   MOV     R0, #Vector_SeriousErrorV	;release SeriousError vector
   ADR     R1, seriousErrorV_handler
   MOV     R2, R12			;R2=pointer to VARS
   SWI     XOS_Release
   MOVVS   R4, R0
 #endif
;MOV R0, #29
;ADR R1, our_UpCallV
;MOV R2, R12
;SWI XOS_Release
 LOCK    R14

 MOVS    R0, R4
 MSRNE   CPSR_f, #1 << 28		;set V
LDMFD   R13!, {R1-R4, PC}


 ._default_MEMC_CR	DCD &36E0D0C

 ._BASICTrans		DCB "BASICTrans", 0
			ALIGN

 ._codelet_os_exit	SWI OS_Exit	;hypervised exit back to OS

 ._codelet1
 SWI     0
 LDR     PC, _codelet1 + 8

 ._codelet2
 NOP					;R1 NOP's for processor vector returns
 NOP					;R2
 LDR     PC, [R13], #4			;R3 hypervised exit back to us

 ._codelet3
 NOP					;R1 NOP's for processor vector returns
 NOP					;R2
 ADD     R13, R13, #4			;R3
 LDR     PC, [R13], #4			;R4 hypervised exit back to us


._set_ADFFS_JIT
 STMFD   R13!, {R0-R4, R14}
 ADR     R1, _val_1
 B       _set_env_variable

 ._val_1 		DCD 1


._unset_ADFFS_JIT
 STMFD   R13!, {R0-R4, R14}
 ADR     R1, _val_0
 B       _set_env_variable

 ._val_0 		DCD 0


._set_env_variable
 ADR     R0, Set_JITStatus
 MOV     R2, #4
 MOV     R3, #0
 MOV     R4, #1				;its a number
 SWI     XOS_SetVarVal			;PRM1-316
LDMFD   R13!, {R0-R4, PC}



;.our_UpCallV
;TEQ R0, #6
;MOVEQ R0, #0
;LDREQ PC, [R13], #4
;MOV PC, R14

.Claim_Undefined_Vector
 LDR     R1, existing_UndefinedInstr
 TEQ     R1, #0					;already claimed
 MOVNE   PC, R14

 STMFD   R13!, {R1-R2, R14}
;MOV R0, #29
;ADR R1, our_UpCallV
;MOV R2, R12
;SWI XOS_Claim
 MOV     R0, #Vector_UndefinedInstr + (1<<8)	;claim Undefined instruction vector
 ADR     R1, Undefined_Instruction_Vector
 SWI     XOS_ClaimProcessorVector		;PRM5a-30
 TEMP    R2
 STRVC   R1, existing_UndefinedInstr
 LOCK    R2
LDMFD   R13!, {R1-R2, PC}
