;Entry_Cache
;-----------
;Handle *Cache On/Off whilst the JIT is running in ARMv4 mode (StrongARM)

.Entry_ADFCache
 STMFD   R13!, {R2-R4, R14}
 LDR     R12, [R12, #0]

 LDRB    R3, [R12, #JIT_ARM4 - VARS]
 TEQ     R3, #0				;ARMv4 mode?
 LDMEQFD R13!, {R2-R4, PC}		;NO

 BL      On_Off_Option
 ADD     R0, R0, #1			;reverse value
 ORR     R3, R3, R0, LSL #31		;0=cache on  1=cache off
 STR     R3, [R12, #JIT_ARM4 - VARS]
 MOV     R2, #page_zero_Scratch_Space	;flush all JIT memory
 RSB     R4, R2, #jit_appspace_end
 BL      hv_reset_memory_block
LDMFD   R13!, {R2-R4, PC}
