.vector_handler_7
 TEQ     R0, #21			;OS_Word 21?
 BEQ     os_word_21			;YES

 #if JIT_debug == 1 AND compile_IOMD == 1
   TEQ     R0, #22			;OS_Word 22?
   BNE     vector_handler_forward	;NO
  
   LDRB    R12, [R1, #0]		;Type
   TST     R12, #%10			;Hardware address?
   BEQ     vector_handler_forward	;NO
   LDRB    R12, [R1, #1]
   LDRB    R14, [R1, #2]
   ORR     R12, R12, R14, LSL #8
   LDRB    R14, [R1, #3]
   ORR     R12, R12, R14, LSL #16
   LDRB    R14, [R1, #4]
   ORR     R12, R12, R14, LSL #24
   TEMP    R14
   STR     R12, MEMC_Vinit
   LOCK    R14
 #endif

;   LDR     R14, _last_address
;   TEQ     R12, R14			;are we changing banks?
;   BEQ     vector_handler_forward	;NO
;   STR     R12, _last_address
;   LDR     R12, force_vsync
;   TEQ     R12, #0			;are we forcing VSyncs?
;   BEQ     vector_handler_forward	;NO, exit
;
;   LDR     R12, os_byte_19_happened
;   TEQ     R12, #0			;do we need to frame pace?
;   BNE     vector_handler_forward	;NO, exit
;   STMFD   R13!, {R0-R2}
;   SUB     R13, R13, #4*4
;   MOV     R12, R13			;_SPSR block
;   MOV     R0, #19			;YES, force a VSync to add delay
;   BL      hv_pre_SWI_veneer		;call SWI that follows
;   SWI     XOS_Byte
;   BL      dontexit_SWI_veneer
;   ADD     R13, R13, #4*4
;   MOV     R0, #0
;   TEMP    R1
;   STR     R0, os_byte_19_happened	;look for a vsync
;   LOCK    R1
;   LDMFD   R13!, {R0-R2}

B       vector_handler_forward		;hand back to OS

;._last_address DCD 0