;References:
;swi - vector_handler_forward

;R12, R14 are on the stack


;vector_handler_1A
;-----------------
;OS_UpdateMEMC

.vector_handler_1A
 LDR     R12, [R13, #4]			;pull entry address from stack
 #if compile_RO == 400
   BIC     R12, R12, #&FC000003
 #endif
 BL      ADFFS_internal_check		;is it us?
 BEQ     _P1				;YES

 CMP     R12, #jit_slotsize		;is it RISCOS?
 BHS     vector_handler_forward		;YES, pass on

 #if JIT_WIMP_support == 1
   BL      check_task_ID		;is the task supported?
   BNE     vector_handler_forward	;NO, hand to OS
 #endif

 ._P1
 STMFD   R13!, {R2-R4, R7}

 MOV     R4, R1				;store mask for update on exit

 ADR     R7, MEMC_registers		;R7=MEMC register table
 LDR     R3, [R7, #MEMC_CR << 2]	;R3=current MEMC register value
 AND     R0, R0, R1			;R0 AND R1
 MVN     R2, #0
 EOR     R1, R1, R2			;NOT R1
 AND     R3, R3, R1			;oldMEMC AND NOT R1
 ORR     R0, R3, R0			;(oldMEMC AND NOT R1) OR (R0 AND R1)

 #if compile_IOMD == 1
   LDR     R2, IOMD_addr		;R2 = IOMD chip address
 #endif
 MOV     R3, #MEMC_CR
 BL      update_MEMC			;perform the write

 LDR     R0, [R7, #MEMC_CR << 2]
 BIC     R0, R0, #%111111111 << 17		;clear MEMC register
 ORR     R0, R0, #&3600000 + (MEMC_CR << 17)	;add in MEMC addr and CR reg
 LDR     R1, _mask
 STR     R4, _mask
 LDMFD   R13!, {R2-R4, R7}
B       vector_handler_trap

 ._mask DCD 0				;previous MEMC field mask
