;Branch handler
;
;Addresses we need to translate
; 1F033C0            - SWI dispatch entry point


;Entry:
;R0  = instruction
;R7  = original instruction address + 8
;R14 = re-interpreted instruction address + 8

;i_B
;---
;checks for a breakpoint and adds the branch to the branch prediction table

; B <breakpoint trigger>

ALIGN   32, 4
.i_B
 MOV     R2, R0, LSL #8			;R0=PC relative offset in top bits
 ADD     R3, R14, R2, ASR #6		;R3=destination address in JIT space
 SUB     R4, R3, #jit_code_start	;R4=actual address

 CMP     R4, #jit_appspace_end		;jumping to appspace?
 BHS     i_B_check_address		;NO, we need to check in more detail

 #if JIT_predictive_branching == 1
   PREDICT_BRANCH R3			;YES, add to branch prediction table

   AND     R1, R0, #OP_condition	;get the condition
   TEQ     R1, #OP_AL			;unconditional?
   BEQ     i_copy_and_exit		;YES, exit to branch prediction
  B       i_copy_instruction		;NO, continue processing
 #endif
 #if JIT_predictive_branching == 0
  B       i_copy_and_exit
 #endif

 .i_B_check_address
 MOV     R2, #RO3xx_SWI_Dispatcher
 TEQ     R4, R2				;jumping to the SWI dispatcher?
 MOVEQ   R1, #&C			;ADFF500C
 BEQ     JIT_report_unimplemented	;YES, report (Slappit)

 #if JIT_allow_Breakpoints == 0 AND compile_RO > 311
   CMP     R4, #jit_code_start		;is it a managed entry/exit address?
   MOVHS   R1, #&13			;NO, ADFF5013
   BHS     JIT_report_unimplemented	; |+ report illegal branch
 #endif
					;must be a codelet
 SUB     R2, R4, R14			;correct address to be relative to R14
 BIC     R2, R2, #%111111 << 26
 AND     R0, R0, #%11111111 << 24	;instruction with condition
 ORR     R0, R0, R2, LSR #2		;add in corrected address

B       i_copy_and_exit_handled
