#set jit_allocate_memory = 8 * 1024 * 1024	;total memory for JIT
#set jit_RMA_size	 = 1.5 * 1024 * 1024	;total memory for JIT RMA
#set jit_slotsize	 = 27.5 * 1024 * 1024	;ram to allocate for appspace
#set jit_code_start	 = jit_slotsize - (jit_allocate_memory + jit_RMA_size)
#if compile_RO > 311 AND compile_RO < 450
  #set jit_ram		 = jit_slotsize		;total ram for WimpSlot
#else
  #set jit_ram		 = &1F08000		;total ram for WimpSlot
#endif

#set jit_appspace_end	 = jit_allocate_memory + jit_RMA_size
						;max RAM JIT supports
						;16mb is theorical max
#set jit_RMA_heap	 = jit_allocate_memory	;start of JIT RMA

#set lastfree_codelet	 = jit_appspace_end	;last free block in codelets



.Entry_GOARM3JIT
 STMFD   R13!, {R0-R12, R14}		;preserve all registers for exit
 ADR     R12, VARS

 TEQ     R1, #0				;are we initialising?
 BNE     _P1				;YES

 LDR     R0, jit_code			;NO, shutting down
 TEQ     R0, #0				;is the JIT running?
 LDMEQFD R13!, {R0-R12, PC}		;NO, exit

 #if Managed_ChannelHandler == 1
   BL      reset_sound_configure	;reset audio subsystem
 #endif
 #if JIT_debug == 0
   BL      kill_26bit_modules		;kill legacy modules
 #endif
 MOV     R8, #&20
 MOV     R9, #jit_code_start
 BL      kill_voices_in_range		;kill any voices
 BL      kill_vectors_in_range		;kill any rogue vectors
 BL      clear_jitmemorya		;remove any claimed memory

 #if JIT_debug == 1 AND compile_IOMD == 1
   ADR     R0, report_JIT_IOMD
   MOV     R1, #0
   SWI     XOS_RemoveTickerEvent
 #endif

 MOV     R1, #0
 BL      Entry_ADFRemapVideoMemory	;shutdown the abort handlers

 #if JIT_dont_reinit_BASIC == 0 AND compile_RO > 311 AND Private_BASIC == 0
   MOV     R0, #Module_Delete		;RMKill BASIC module
   ADR     R1, _BASICModule
   SWI     XOS_Module			;PRM1-235
   MOV     R0, #Module_ReInit		;RMReInit BASIC module
   SWI     XOS_Module			;PRM1-234
 #endif

 BL      release_ChangeEnvironmentV	;release environment handlers

 MOV     R0, #Vector_IRQ		;release Data abort
 LDR     R1, existing_IRQVector
 ADR     R2, IRQ_Vector_Handler
 SWI     XOS_ClaimProcessorVector	;PRM5a-30

 MOV     R0, #Vector_BranchThruZero	;release branch through zero handler
 LDR     R1, existing_Branch_thru_zero
 ADR     R2, Branch_thru_zero
 SWI     XOS_ClaimProcessorVector	;PRM5a-30

 TEMP    R1
 MOV     R0, #0
 STR     R0, jit_code
 STR     R0, JIT_event11_active		;reset Event 11 counter
 LOCK    R1

 #if JIT_protect_page_zero == 1
   LDR     R0, os_version		;ARM710VE-83 / 85
   CMP     R0, #&380 << 8		;are we below RO3.8?
   LDRLO   R1, page_zero_L2PT		;YES, restore page zero protection
   MOVLO   R0, #0			; |
   BLLO    CACHEOP_INVALIDATE_TLB_R0	; |+ flush TLB
 #endif

 #if compile_RO == 500
   TEMP    R1
   ADR     R2, Current_Machine_State
   LDR     R0, [R2, #Machine_State.cpu_control_register]
   TEQ     R0, #0			;did we change the CPU CR?
   MCRNE   P15, 0, R0, C1, C0, 0	;YES, set it back
   MOVNE   R0, #0
   STRNE   R0, [R2, #Machine_State.cpu_control_register]
   LOCK    R1
   #if compile_RO == 500 AND High_Vectors == 1
;ref. https://www.riscosopen.org/wiki/documentation/show/OS_Memory%2020
     MOV     R0, #20			;check compatibility page
     LDR     R1, [R2, #Machine_State.OS_Memory20]
     TEQ     R1, #0			;did we change it?
     SWINE   XOS_Memory			;YES
   #endif
 #endif

 BL      shutdown_interrupts

 #if Private_BASIC == 1
   LDR     R0, [R12, #BASICTrans_loaded - VARS]
   TEQ     R0, #0
   MOVNE   R0, #Module_Delete		;RMKill BASIC module
   ADRNE   R1, _BASICTrans
   SWINE   XOS_Module			;PRM1-235
   MOV     R0, #0
   STR     R0, [R12, #BASICTrans_loaded - VARS]
 #endif

 #if JIT_self_modifying_support == 1 AND JIT_debug == 0
   BL      reset_appspace_L2PT
 #endif

 SUBS    R0, R0, R0			;clear V
LDMFD   R13!, {R0-R12, PC}


 ._P1
 #if JIT_debug == 1 AND compile_IOMD == 1
   MOV     R0, #dbg_pause_default
   TEMP    R1
   STR     R0, dbg_pause
   LOCK    R1

   MOV     R0, #1
   ADR     R1, report_JIT_IOMD
   MOV     R2, #0
   SWI     XOS_CallEvery
 #endif

 LDR     R0, jit_code
 TEQ     R0, #0				;is the JIT already setup?
 BNE     _already_setup			; |+ skip initialisation

 BL      store_machine_state		;store key repeat etc
 
 MVN     R0, #0				;read current slotsize
 MVN     R1, #0
 SWI     XWimp_SlotSize			;PRM3-203

 MOV     R1, #jit_allocate_memory - &8000	;RAM limit
 CMP     R0, R1				;do we have enough RAM?
 MOVHS   R3, R1				;cap at jit_ram limit
 MOVLO   R3, R0				;store current slotsize
 MOV     R1, #jit_ram - &8000
 CMP     R0, R1				;do we have enough RAM?
 MOVLO   R0, R1				;NO, allocate more
 MVNLO   R1, #0
 SWILO   XWimp_SlotSize			;PRM3-203
 ADDVS   R13, R13, #4			;drop R0 from stack
 LDMVSFD R13!, {R1-R12, PC}		;exit on error

 MVN     R0, #0				;read current slotsize
 MVN     R1, #0
 SWI     XWimp_SlotSize			;PRM3-203
 MOV     R1, #jit_ram - &8000
 CMP     R0, R1				;do we have enough RAM?
 MOVLO   R0, #1 << 31			;NO, set V
 ADDLOS  R0, R0, R0
 ADRVS   R0, Error_jit_slotsize
 ADDVS   R13, R13, #4			;drop R0 from stack
 LDMVSFD R13!, {R1-R12, PC}		;exit on error
 TEMP    R0
 STR     R3, pre_JIT_wimp_slot_size	;store current WimpSlot
 LOCK    R0

 MOV     R0, #Heap_Initialise		;initialise JIT RMA heap
 MOV     R1, #jit_RMA_heap
 MOV     R3, #jit_RMA_size
 SWI     XOS_Heap			;PRM1-377

 ADR     R7, MEMC_registers		;reset MEMC registers
 MOV     R0, #&1F03800
 STR     R0, [R7, #IOC_Cinit << 2]	;Pointer
 MOV     R0, #&36E0D0C
 STR     R0, [R7, #MEMC_CR << 2]

 MOV     R0, #0
 TEMP    R1
 STR     R0, Module_being_inserted
 LOCK    R1
 #if compile_GPU == 1
   ADR     R7, IOC_registers		;initialise IOC registers
   MOV     R1, #&80 >> 2
   ._IOC_L1
     SUBS    R1, R1, #4
     STR     R0, [R7, R1]
   BNE     _IOC_L1

   MOV     R2, #IOC_IRQA_init		;initialise IOC IRQA
   STRB    R2, [R7, #IOC_IRQA_mask >> 2]
   MOV     R2, #IOC_IRQB_init		;initialise IOC IRQB
   STRB    R2, [R7, #IOC_IRQB_mask >> 2]
   MOV     R2, #IOC_CR_init		;initialise IOC CR
   STRB    R2, [R7, #IOC_CR >> 2]
   ADR     R1, T0_value
   MOV     R2, #20000			;reset T0/T1 to default values
   STR     R2, [R1, #T0_latch - T0_value]
   STR     R2, [R1, #T0_value - T0_value]
   MOV     R2, #&10000000
   STR     R2, [R1, #T1_latch - T0_value]
   STR     R2, [R1, #T1_value - T0_value]
 #endif

 TEMP    R1
 STR     R0, linear_handler_entry	;reset sound handler
 LOCK    R1

 ADR     R7, jit_claimed_vectors	;initialise Vectors
 MOV     R1, #max_vectors_to_track * vector_table.size
 ._vectors_L1
   STR     R0, [R7], #4
   SUBS    R1, R1, #4
 BNE     _vectors_L1

 ADR     R7, DeviceVectors		;initialise Device Vector claims
 MOV     R1, #(last_device_to_track + 1) * device_table.size
 ._device_vectors_L1
   STR     R0, [R7], #4
   SUBS    R1, R1, #4
 BNE     _device_vectors_L1

 ADR     R2, Current_Machine_State
 #if Unaligned_Support == 0
   MRC     P15, 0, R0, C1, C0, 0	;get CPU control register
					;see ARM ARM rev.I B3-12
   BIC     R3, R0, #1 << 1		;disable alignment fault checking
   BIC     R3, R3, #1 << 22		;enable rotated unaligned loads
   TEQ     R0, R3
   TEMP    R1
   STRNE   R0, [R2, #Machine_State.cpu_control_register]
   LOCK    R1
   MCRNE   P15, 0, R3, C1, C0, 0	;update ARM Control Register
 #endif
 #if Unaligned_Support == 1
   MRC     P15, 0, R0, C1, C0, 0	;get CPU control register
					;see ARM ARM rev.I B3-12
   ORR     R3, R0, #1 << 1		;enable alignment fault checking
   TEQ     R0, R3
   TEMP    R1
   STRNE   R0, [R2, #Machine_State.cpu_control_register]
   LOCK    R1
   MCRNE   P15, 0, R3, C1, C0, 0	;update ARM Control Register
 #endif

 #if compile_RO == 500 AND High_Vectors == 1
;ref. https://www.riscosopen.org/wiki/documentation/show/OS_Memory%2020
   MOV     R0, #20			;check compatibility page
   MVN     R1, #0
   SWI     XOS_Memory
   MOVVS   R1, #0
   CMP     R1, #0			;is it available?
   MOVMI   R1, #0			;NO
   STR     R1, [R2, #Machine_State.OS_Memory20]
   TEQ     R1, #1			;is page zero mapped?
   MOVEQ   R1, #0			;YES
   SWIEQ   XOS_Memory			; |+ disable page
 #endif

 #if JIT_protect_page_zero == 1
   LDR     R0, os_version		;ARM710VE-83 / 85
   CMP     R0, #&380 << 8		;are we below RO3.8?
   TEMP    R3
   LDRLO   R0, L2PT_addr		;YES, protect page zero
   LDRLO   R1, [R0]			; |  page zero L2PT
   STRLO   R1, page_zero_L2PT		; |  keep a copy for later
   BICLO   R1, R1, #%11111111 << 4	; |  user is read-only
   ORRLO   R1, R1, #%11101010 << 4	; |  protect 0..&2FFF
   MOVLO   R0, #0			; |
   BLLO    CACHEOP_INVALIDATE_TLB_R0	; |+ flush TLB
   LOCK    R3
 #endif

 #if JIT_instruction_trace == 1
   B       _skip_name
   ._instruction_trace_name DCB "ADFFS Instruction Trace",0
   ALIGN
   ._skip_name
   LDR     R3, [R12, #IT_DA_address - VARS]
   TEQ     R3, #0
   BNE     _IT_DA_created
   MOV     R0, #&1000000
   STR     R0, [R0, #-4]

   MOV     R2, #&200000					;initial size
;                +----------- requires specific physical pages
;                |+---------- area can't be dragged in task bar
;                ||+--------- area is doubly mapped
;                |||+-------- area is not cacheable
;                ||||+------- area is not bufferable
;                |||||++++--- access privileges (2=supervisor only)
   MOV     R4, #%010000000
   MOV     R5, R2				;max area size
   MOV     R6, #0				;DA handler pointer
   ADR     R8, _instruction_trace_name		;pointer to our DA name
   MOV     R0, #0				;Create DA PRM5a-55
   MVN     R1, #0				;area number
   MVN     R3, #0				;logical base of area
   MOV     R7, #0				;workspace pointer
   SWI     XOS_DynamicArea			;PRM5a-55
   STR     R1, [R12, #our_IT_DA_number - VARS]	;our DA
   STR     R3, [R12, #IT_DA_address - VARS]	;our DA address
   ._IT_DA_created
   MOV     R1, #&100000
   SUB     R1, R1, #1
   ADD     R3, R3, R1
   BIC     R3, R3, R1				;align to 1MB boundary
   MOV     R0, #instruction_trace_ptr
   STR     R3, [R0, #-4]
 #endif

					;Now setup the top 16mb ready for
					;translated code, which needs to
					;jump back into the JIT
 MOV     R3, #jit_code_start
 LDR     R1, branch_to_jit		;instruction to enter JIT
 MOV     R2, R1, LSL #4
 TEMP    R7
 STR     R2, branch_to_jit_no_condition	;used to quickly check for Hypercalls
 LOCK    R7
 MOV     R2, R1
 MOV     R4, R1
 MOV     R5, R1
 MOV     R6, R1
 MOV     R7, R1
 MOV     R8, R1
 MOV     R0, R1
 ._L2
   STMIA   R3!, {R0-R2, R4-R8}
   STMIA   R3!, {R0-R2, R4-R8}
   TEQ     R3, #jit_slotsize
 BNE     _L2

 #if compile_DEBUG == 1 OR JIT_instruction_trace == 1	;force chocolate off
   MOV     R3, #&4000
   LDR     R4, current_PageSize
   MOV     R1, #jit_ram - &4000
   ._L1_chocolate
     LDR     R0, [R3], R4		;force pages to be mapped
     SUBS    R1, R1, R4
   BGT     _L1_chocolate
 #endif

 TEMP    R1
 LDR     R0, OIRQ_vector_stack		;reset private stacks
 STR     R0, IRQ_vector_stack
 LDR     R0, Otmp_module_stack
 STR     R0, tmp_module_stack
 LOCK    R1

 MVN     R0, #0
 MOV     R1, #1				;don't change MODE or DA2 size
 BL      Entry_ADFRemapVideoMemory	;start the abort vectors

#if Private_BASIC == 0
					;************************************
					;move BASIC into RMA and fix-up
					;USR and CALL commands
					;************************************
					;Ensure BASIC is the ROM version
 MOV     R0, #Module_Delete		;RMKill BASIC module
 ADR     R1, _BASICModule
 SWI     XOS_Module			;PRM1-235
 MOV     R0, #Module_ReInit		;RMReInit BASIC module
 SWI     XOS_Module			;PRM1-234

 MOV     R0, #Module_Lookup		;find BASIC module
 ADR     R1, _BASICModule
 SWI     XOS_Module			;PRM1-249
 BVS     _no_BASIC
 SUB     R11, R3, #4			;R11=pointer to BASIC module
 LDR     R3, [R11]			;R3=size of BASIC module
 ADD     R3, R3, #4			;need an extra word for the module size
 MOV     R0, #Heap_Claim		;claim JIT RMA space for BASIC
 MOV     R1, #jit_RMA_heap
 SWI     XOS_Heap			;PRM1-379
 BVS     _no_BASIC
					;R2=address of block
 ADR     R10, _BASICModule_var1
 LDMIA   R10, {R4, R5, R6, R7, R8, R9, R10}
 ._copy_BASIC_L1			;copy BASIC rom to our RMA space
   LDR     R0, [R11, R3]
   TEQ     R0, R9
   TEQNE   R0, R10
   ADDEQ   R0, R0, #JIT_SWI_OS_Flag << 20	;trigger our SWI handler

   ADD     R14, R2, R3
   TEQ     R0, R4			;1st instruction match?
   BNE     _copy_BASIC_P1		;NO

   LDR     R1, [R14, #4]
   AND     R1, R1, R6			;mask to leave <alu> PC, R14, ...
   TEQ     R1, R5			;2nd instruction match?
   BNE     _copy_BASIC_P1		;NO

   LDR     R1, [R14, #8]
   TEQ     R1, R7			;3rd instruction match?
   TEQNE   R1, R8			;3rd instruction match?
   BNE     _copy_BASIC_P1

   LDR     R1, _BASICModule_SWI		;replacement instruction
   STR     R1, [R14, #8]
   ._copy_BASIC_P1
   LDR     R1, _BASICModule_var2	;check for SYS
   TEQ     R0, R1			;instruction match?
   LDREQ   R0, _BASICModule_SWI2	;YES
   STR     R0, [R2, R3]

   SUBS    R3, R3, #4
 BPL     _copy_BASIC_L1

 MOV     R3, R2				;preseve R2
 MOV     R0, #Module_InsertFromMemoryToRMA
 ADD     R1, R2, #4			;module start
 LDR     R2, [R2, #0]			;module size
 SWI     XOS_Module			;PRM1-242
 MOV     R4, R2				;R4=size

 MOV     R0, #Heap_Free
 MOV     R2, R3				;free block we just claimed
 MOV     R1, #jit_RMA_heap
 SWI     XOS_Heap			;PRM1-380
 ._no_BASIC
					;************************************
#endif
 #if JIT_WIMP_support == 1
   BL      get_taskID			;get current task
 #endif

 TEMP    R3
 MOV     R0, #0				;reset hypervised IRQ handlers
 STR     R0, hypervised_IRQ1V
 STR     R0, hypervised_IRQv
 #if JIT_debug == 1
   STR     R0, jit_codelet_count
 #endif

 MOV     R0, #Vector_IRQ + (1<<8)	;claim IRQ vector
 ADR     R1, IRQ_Vector_Handler
 SWI     XOS_ClaimProcessorVector	;PRM1-66
 STR     R1, existing_IRQVector		;store existing

 MOV     R0, #Vector_BranchThruZero + (1<<8)	;claim vector
 ADR     R1, Branch_thru_zero
 SWI     XOS_ClaimProcessorVector	;PRM5a-30
 STR     R1, existing_Branch_thru_zero	;store existing

 SWI     XOS_GetEnv			;get EnvString
 STR     R0, page_zero_EnvString	;used in page_zero_abort handler
 STR     R2, page_zero_EnvTime		;used in page_zero_abort handler
					;setup exit code below 27.5mb
 MOV     R0, #jit_code_start
 LDR     R1, _codelet_os_exit		;OS_Exit for general use
 STR     R1, [R0, #-4]!
 STR     R0, jit_managed_os_exit

 ADR     R5, _codelet3			;LDR PC, [R13], #4 for general use
 LDMIA   R5, {R1-R3}
 STMDB   R0!, {R1-R3}			;entry for us
 ADD     R1, R0, #8			;skip the two NOP's
 STR     R1, jit_managed_ldr_pc_r13

 ADR     R5, _codelet3_2		;LDR PC, [R13+4], #4 for general use
 LDMIA   R5, {R1-R4}
 STMDB   R0!, {R1-R4}			;entry for us
 ADD     R1, R0, #8			;skip the two NOP's
 STR     R1, jit_managed_ldr_pc_r13_2
 SUB     R1, R1, #&18 + 8
 MOV     R1, R1, LSR #2
 ORR     R1, R1, #&EA000000		;B <address>
 STR     R1, jit_managed_IRQ_entry	;instruction game sees at &18

#if Private_BASIC == 0
 LDR     R2, _codelet_BASIC		;allocate space for BASIC's param table
 SUB     R0, R0, #31 * 4		;space for jump table
 MOV     R1, #31
 ._BASIC_entry_L1
   STR     R2, [R0, #-4]!
   SUBS    R1, R1, #1
 BNE     _BASIC_entry_L1
 STR     R0, jit_managed_BASIC_entry
 SUB     R0, R0, #4			;extra word for BASIC version no.
#endif
 SUB     R0, R0, #256+4+4		;space for error buffer
 STR     R0, env_handler_buffer
 SUB     R0, R0, #17 * 4		;space for registers
 STR     R0, env_handler_registers
 SUB     R0, R0, #8 * EnvHandler.size	;space to track handlers
 STR     R0, environment_handlers

 ADR     R2, previous_env_handler6	;managed entry to previous handler
 ADR     R3, previous_env_handler7
 ADR     R4, previous_env_handler8
 ADR     R5, previous_env_handler9
 ADR     R6, previous_env_handler10
 ADR     R7, previous_env_handler11
 ADR     R8, previous_env_handler12
 ADR     R9, previous_env_handler16
 ADR     R1, _codelet_previous_EnvHandlers
 STMDB   R0!, {R2-R9}
 LDMIA   R1, {R2-R9}
 STMDB   R0!, {R2-R9}
 STR     R0, managed_EnvironmentHandlers
 BL      reset_ChangeEnvironmentV

#if Private_CLib == 1
 MOV     R1, #0
 STR     R1, [R0, #-4]!
 STR     R0, private_CLibCounter
 STR     R1, [R0, #-4]!
 STR     R0, private_RISCOSLibWord
 STR     R1, [R0, #-4]!
 STR     R0, private_CLibWord
#endif
					;-----------------------
 SUB     R0, R0, #codelet_struct.codelet	;initialize first codelet
 BIC     R0, R0, #codelet_alignment - 1		;align it
 STR     R0, [R0, #codelet_struct.next]		;next=pointer to itself
 STR     R0, [R0, #codelet_struct.previous]	;previous=pointer to itself
 MOV     R1, #codelet_struct.codelet
 STR     R1, [R0, #codelet_struct.size]		;size=codelet_struct size
 MVN     R1, #0
 STR     R1, [R0, #codelet_struct.source]	;source=-1
 STR     R0, first_codelet
						;initialize last free codelet
 MOV     R2, #lastfree_codelet			;R2=codelet
 STR     R2, [R2, #codelet_struct.next]		;next=pointer to itself
 STR     R2, [R2, #codelet_struct.previous]	;previous=pointer to itself
 MOV     R1, #0
 STR     R1, [R2, #codelet_struct.source]	;source=0
 SUB     R1, R0, R2				;R1=size
 STR     R1, [R2, #codelet_struct.size]		;size=free space
					;-----------------------
 MOV     R0, #jit_code_start
 STR     R0, jit_code			;start of translated code
 LOCK    R3

 ._already_setup
 LDR     R1, [R13, #0]			;command tail
 MOV     R0, #16			;base 16 number with restricted range
 SWI     XOS_ReadUnsigned		;read the value PRM1-460
 ADDVS   R13, R13, #4			;drop R0 from stack
 LDMVSFD R13!, {R1-R12, PC}		;exit on error
 ADD     R4, R2, #jit_code_start	;R4=start address

 MOV     R3, R1				;do we have an environment string?
 ._find_env_L1
   LDRB    R1, [R3], #1
   TEQ     R1, #ASC(";")		;environment string?
   TEQNE   R1, #0			;terminator?
 BNE     _find_env_L1			;NO

 TEQ     R1, #ASC(";")			;environment string found?
 BNE     _find_env_P1
 SWI     XOS_GetEnv			;PRM1-301
 MOV     R1, R2				;R1=time
 MOV     R0, R3				;string to become environment
 SWI     XOS_WriteEnv			;PRM1-322

 ._find_env_P1
 MOV     R2, R4				;preserve R2
 TEQ     R2, #jit_code_start		;are we simply setting up the JIT?
 LDMEQFD R13!, {R0-R12, PC}		;YES, exit

 ADD     R13, R13, #3 * 4		;drop R0-R2 from stack
 LDMFD   R13!, {R3-R6}			;stack is now: R7-R12, R14
 LDMFD   R13!, {R7-R12}			;clear down stack
 ADD     R13, R13, #4			;drop R14

 MRS     R14, CPSR			;go into the correct USER mode
 BIC     R14, R14, #%11001111		;USER/USER32 IRQ/FIQ enabled
 MSR     CPSR_all, R14
 #if compile_IOMD == 1
   NOP
 #endif

 MOV     R13, #jit_allocate_memory	;put stack at end of user space
 LDR     R14, jit_managed_os_exit
MOV     PC, R2				;call code, R0=environment string


#if Private_BASIC == 0
 ._BASICModule		DCB "BASIC", 0
			ALIGN

 ._BASICModule_var1	LDMIA R0, {R0-R7}	;R4 instr. to find in BASIC
			DCD &E00FE000		;R5 ADR R14, ...
			DCD &F00FF000		;R6 mask for it
			LDMIA R13!, {PC}	;R7 USR / CALL jump routine
			LDR PC, [R13], #4	;R8 alternative jump routine
						;---------
			SWI OS_GetEnv		;R9 hypervise this
			SWI XOS_GetEnv		;R10 ..and this
						;replace instruction above
						;with the one below
 ._BASICModule_SWI	SWI ADFFS_BASICCall + (JIT_SWI_OS_Flag << 20)

;NOTE: See /castle/RiscOS/Sources/Programmer/BASIC/s/Stmt2
;      function: CALLARMROUT (line 1901 in v1.15)
						;---------

 ._BASICModule_var2	MOV PC, R11
						;---------
 ._BASICModule_SWI2	SWI ADFFS_BASICSys + (JIT_SWI_OS_Flag << 20)

;NOTE: See /castle/RiscOS/Sources/Programmer/BASIC/s/Stmt2
;      function: SYSCALL (line 1779 in v1.15)
						;---------
 ._codelet_BASIC
 LDR     PC, [PC, #&74]			;31*2 + 1 instructions
#endif

#if Private_BASIC == 1
 ._BASICTrans		DCB "BASICTrans", 0
			ALIGN
#endif

 ._codelet_os_exit	SWI OS_Exit	;hypervised exit back to OS



 ._codelet3
 NOP					;R1 NOP's for processor vector returns
 NOP					;R2
 LDR     PC, [R13], #4			;R3 hypervised exit back to us

 ._codelet3_2
 NOP					;R1 NOP's for processor vector returns
 NOP					;R2
 ADD     R13, R13, #4			;R3
 LDR     PC, [R13], #4			;R4 hypervised exit back to us

  ._codelet_previous_EnvHandlers
 LDR     PC, [PC, #(8-2) * 4]		;branch to our managed entry 6
 LDR     PC, [PC, #(8-2) * 4]		;branch to our managed entry 7
 LDR     PC, [PC, #(8-2) * 4]		;branch to our managed entry 8
 LDR     PC, [PC, #(8-2) * 4]		;branch to our managed entry 9
 LDR     PC, [PC, #(8-2) * 4]		;branch to our managed entry 10
 LDR     PC, [PC, #(8-2) * 4]		;branch to our managed entry 11
 LDR     PC, [PC, #(8-2) * 4]		;branch to our managed entry 12
 LDR     PC, [PC, #(8-2) * 4]		;branch to our managed entry 16
