JIT Phase 1

Discuss development specific to the Pi version of ADFFS
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JIT Phase 1

Post by JonAbbott » Sat Dec 14, 2013 11:04 am

The aim is to re-interpret all instructions that are PC relative into codelets, that correct PC to the original address space and get code running on ARM610:

LDR Rd, [PC, ...] (coded)
LDR Rd, [PC, Rm] (where Rd = Rm) (coded)
LDR PC, [Rx, ...] (coded)
LDR PC, [PC, ...] (coded)

STR Rd, [PC, ...] (coded)
STR PC, [Rx, ...] (coded)
STR PC, [PC, ...] (coded)
STR Rd, [Rn, ...]! (where Rd = Rn < 15)
STR Rd, [Rn], ... (where Rd = Rn < 15)

ALU instructions except MOV and MVN:
ADD{S} Rd, PC, ... (coded)
ADD{S} Rd, PC, Rm, <shift> Rs (where Rd = Rs) (coded)
ADD{S} Rd, Rn, PC, <shift expression> (coded)

and ones with PC in Rd:
ADD PC, Rx, ... (coded)
ADD PC, PC, ... (coded)
ADDS PC, Rx, ... (coded)
ADDS PC, PC, ... (coded)

MOV/MVN Rd, PC (coded)
MOV/MVN Rd, PC, <shift> ... (coded)
MOV/MVN Rd, PC, <shift> Rs (where Rd = Rs) (coded)

MOV/MVN PC, Rm ... (coded)
MOVS/MVNS PC, Rm ... (coded)
MOV{S} PC, #<immediate> (coded)
MOV{S} PC, PC (coded) (copies the instruction without the S bit)

BL <offset> (coded)

LDM<mode> Rn{!}, {..., PC} (coded)
LDM<mode> Rn{!}, {..., PC}^ (coded)
LDM<mode> PC, {reg_list} (coded)

STM<mode> Rn{!}, {..., PC} (coded)
STM<mode> PC, {reg_list} (coded)

TEQ Rn, PC (coded) (used by No Excuses)

Rare, if unlikely instructions covered by this include instructions using PC in Rm (which may contain the PSR flags - check on physical):
LDR Rd, [Rn, PC] (used by Tactic)
STR Rd, [Rn, PC]
LDR/STR Rd, [PC, #<immed>]! (stores value at PC+<immed> then jumps to PC+<immed>) (used by KerBang!)
LDR/STR Rd, [PC], #<immed> (stores value at PC then jumps to PC+<immed>)
STM<mode> Rn{!}, {..., PC}^
LDM<mode> PC, {..., PC}
STM<mode> PC, {..., PC}

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