JIT codelets

Discuss development specific to the Pi version of ADFFS
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JonAbbott
Posts: 1739
Joined: Thu Apr 11, 2013 12:13 pm
Location: Essex

JIT codelets

Post by JonAbbott » Fri Dec 06, 2013 1:06 pm

Detailed here are instructions that require re-encoding and the codelet equivalent. Note, this is work in progress.

Where:
_PC = original code space PC (ie instruction + 8)
_R14 = next instruction in JIT interpreted code space (ie PC - 4)
application_space_end = 1000000 (ie 16mb - the end of Application space)
jit_code_start = 1380000 (ie 23.5mb - the re-interpreted address space start)


LDR{B}{T} Rd, [PC, ...]

where Rd<PC

Code: Select all

LDR Rd, _PC
LDR Rd, [Rd, ...]
B _R14
._PC DCD 0
where Rd=PC

Code: Select all

STR R0, _tmp
MRS R0, CPSR
STR R0, _cpsr
LDR R0, _PC
LDR R0, [R0, ....]
CMP R0, #application_space_end
ADDLO R0, R0, #jit_code_start
STR R0, _newPC
LDR R0, _cpsr
MSR CPSR_f, R0
LDR R0, _tmp
LDR PC, _newPC
._PC DCD 0
._tmp DCD 0
._newPC DCD 0

STR{B}{T} Rd, [PC, #<immed>]

where Rd=0

Code: Select all

STR R1, _tmp
LDR R1, _PC
STR R0, [R1, #<immed>]
LDR R1, _tmp
B _R14
._PC DCD 0
._tmp DCD 0
where Rd<>0

Code: Select all

STR R0, _tmp
LDR R0, _PC
STR Rd, [R0, #<immed>]
LDR R0, _tmp
B _R14
._PC DCD 0
._tmp DCD 0

STR{B}{T} Rd, [PC, Rm ...]

if (Rd=0 or Rd=1) and (Rm=0 or Rm=1)

Code: Select all

STR R2, _tmp
LDR R2, _PC
STR Rd, [R2, Rm ...]
LDR R2, _tmp
B _R14
._PC DCD 0
._tmp DCD 0
else if Rm=0 or (Rm<>0 and Rd=0)

Code: Select all

STR R1, _tmp
LDR R1, _PC
STR Rd, [R1, Rm ...]
LDR R1, _tmp
B _R14
._PC DCD 0
._tmp DCD 0
else

Code: Select all

STR R0, _tmp
LDR R0, _PC
STR Rd, [R0, Rm ...]
LDR R0, _tmp
B _R14
._PC DCD 0
._tmp DCD 0

STR{B}{T} PC, [Rn, Rm ...]

where (Rm>1 and Rn>1) and Rn!=PC

Code: Select all

STR R0, _tmp0
STR R1, _tmp1
MRS R0, CPSR
AND R1, R0, #&F0000003
AND R0, R0, #%11 << 6
ORR R1, R1, R0, LSL #20
LDR R0, _PC
ORR R1, R1, R0
STR R1, [R0, ...]
LDR R0, _tmp0
LDR R1, _tmp1
B _R14
._PC DCD 0
._tmp0 DCD 0
._tmp1 DCD 0
where (Rm=0 or Rm=1)

Code: Select all

STR R2, _tmp0
STR R3, _tmp1
MRS R2, CPSR
AND R3, R2, #&F0000003
AND R2, R2, #%11 << 6
ORR R3, R3, R2, LSL #20
LDR R2, _PC
ORR R3, R3, R2
STR R3, [R2, ...]
LDR R2, _tmp0
LDR R3, _tmp1
B _R14
._PC DCD 0
._tmp0 DCD 0
._tmp1 DCD 0

<AND, EOR, SUB, RSB, ADD, ADC, SBC, RSC, ORR, BIC>{S} Rd, PC, ...

where Rd<>PC

Code: Select all

LDR Rd, _PC
<AND, EOR, SUB, RSB, ADD,  ADC, SBC, RSC, ORR, BIC>{S} Rd, Rd, ...
B _R14
._PC DCD 0
where Rd=PC

Code: Select all

Yet to be coded

MOV Rd, PC{, <shift>}

where {, shift} = <LSL, LSR, ASR, ROR> Rs and Rs = Rd

Code: Select all

Yet to be coded
if Rd=R0 then Rx=R1 else Rx=R0

Code: Select all

STR Rx, _tmp
MRS Rd, CPSR
AND Rx, Rd, #&F0000003
AND Rd, Rd, #%11 << 6
ORR Rx, Rx, Rd, LSL #20
LDR Rd, _PC
ORR Rd, Rd, Rx
LDR Rx, _tmp
{MOV Rd, Rd, <shift>} - only required if {, <shift>} exists
B _R14
._PC DCD 0

MOV PC, Rm{, <shift>}
if Rd=R0 then Rx=R1 else Rx=R0

Code: Select all

STR Rx, _tmp
MRS Rx, CPSR
STR Rx, _cpsr
LDR Rx, _tmp
MOV Rx, Rx{, <shift>}
BIC Rx, Rx, #&FC000003
CMP Rx, #application_space_end
ADDLO Rx, Rx, #jit_code_start
STR Rx, _PC
LDR Rx, _cpsr
MSR CPSR_f, Rx
LDR Rx, _tmp
LDR PC, _PC
._tmp DCD 0
._PC DCD 0
._cpsr DCD 0

MOVS PC, Rm{, <shift>}
if OS=32bit then os_32bit = 1 << 6 else os_32bit=0

Code: Select all

STR R0, _tmp
MOV R0, Rm{, <shift>}
STR R0, _cpsr
BIC R0, R0, #&FC000003
CMP R0, #application_space_end
ADDLO R0, R0, #jit_code_start
STR R0, _PC
LDR R0, _cpsr
AND R0 ,R0, #&FC000003
ORR R0, R0, R0, LSR #20
BIC R0, R0, #%1111 << 8
BIC R0, R0, #%11 << 26
ORR R0, R0, #os_32bit
MSR CPSR_all, R0
NOP
LDR R0, _tmp
LDR PC, _PC
._cpsr DCD 0
.tmp DCD 0
._PC DCD 0

MOV PC, #<immediate>
Yet to be coded


BL <offset>

Code: Select all

STR R0, _tmp0
STR R1, _tmp1
MRS R0, CPSR
AND R1, R0, #&F0000003
AND R0, R0, #%11 << 6
ORR R1, R1, R0, LSL #20
SUB R14, R14, #jit_code_start
ORR R14, R14, R1
ADR R0, _tmp0
LDR R0, _tmp0
LDR R1, _tmp1
LDR PC, _PC
._PC DCD <original BL address + &1380000)
.tmp0 DCD 0
.tmp1 DCD 0

LDMxx Rn{!}, {PC}
if Rn=0 Rx=1 else Rx=0

Code: Select all

STR Rx, _tmp
LDMxx Rn{!}, {Rx}
STR Rx, _PC
MRS Rx, CPSR
STR Rx, _cpsr
LDR Rx, _PC
BIC Rx, Rx, #&FC000003
CMP Rx, #application_space_end
ADDLO Rx, Rx, #jit_code_start
STR Rx, _PC
LDR Rx, _cpsr
MRS CPSR_f, Rx
LDR Rx, _tmp
LDR PC, _PC
._PC DCD 0
._tmp DCD 0
._cpsr DCD 0

LDMxx Rn{!}, {PC}^
if Rn=0 Rx=1 else Rx=0

Code: Select all

STR Rx, _tmp
LDMxx Rn{!}, {Rx}
STR Rx, _cpsr
BIC Rx, Rx, #&FC000003
CMP Rx, #application_space_end
ADDLO Rx, Rx, #jit_code_start
STR Rx, _PC
LDR Rx, _cpsr
AND Rx ,Rx, #&FC000003
ORR Rx, Rx, Rx, LSR #20
BIC Rx, Rx, #%1111 << 8
BIC Rx, Rx, #%11 << 26
ORR Rx, Rx, #os_32bit
MSR CPSR_all, Rx
NOP
LDR Rx, _tmp
LDR PC, _PC
._PC DCD 0
._tmp DCD 0
._cpsr DCD 0

LDMxx Rn{!}, {<reglist>, PC}
if Rn=0 Rx=1 else Rx=0

Code: Select all

STR Rx, _tmp
DB=LDR Rx, [Rn, #-4]!    DA=LDR Rx, [Rn], #-4   IB=LDR Rx, [Rn, #reglist * 4]   IA=LDR Rx, [Rn, #(reglist - 1) * 4]
STR Rx, _PC
LDR Rx, _tmp
LDMxx Rn{!}, {<reglist>}
STR Rx, _tmp
ADD Rn, Rn, #4 (NOP'd if Rn is in <reglist>)
MRS Rx, CPSR
STR R0, _cpsr
LDR Rx, _PC
BIC Rx, Rx, #&FC000003
CMP Rx, #application_space_end
ADDLO Rx, Rx, #jit_code_start
STR Rx, _PC
LDR Rx, _cpsr
MSR CPSR_f, Rx
LDR Rx, _tmp
LDR PC, _PC
._PC DCD 0
._tmp DCD 0
._cpsr DCD 0

LDMxx Rn{!}, {<reglist>, PC}^
if Rn=0 Rx=1 else Rx=0

Code: Select all

STR Rx, _tmp
DB=LDR Rx, [Rn, #-4]!    DA=LDR Rx, [Rn], #-4   IB=LDR Rx, [Rn, #reglist * 4]   IA=LDR Rx, [Rn, #(reglist - 1) * 4]
STR Rx, _cpsr
LDR Rx, _tmp
LDMxx Rn{!}, {<reglist>}
STR Rx, _tmp
ADD Rn, Rn, #4 (NOP'd if Rn is in <reglist>)
LDR Rx, _cpsr
BIC Rx, Rx, #&FC000003
CMP Rx, #application_space_end
ADDLO Rx, Rx, #jit_code_start
STR Rx, _PC
LDR Rx, _cpsr
AND Rx ,Rx, #&FC000003
ORR Rx, Rx, Rx, LSR #20
BIC Rx, Rx, #%1111 << 8
BIC Rx, Rx, #%11 << 26
ORR Rx, Rx, #os_32bit
MSR CPSR_all, Rx
NOP
LDR Rx, _tmp
LDR PC, _PC
._PC DCD 0
._tmp DCD 0
._cpsr DCD 0

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