Search found 174 matches

by steve3000
Tue Jul 29, 2014 8:57 am
Forum: ADFFS
Topic: IOC device 9 (Sound Buffer Change)
Replies: 9
Views: 1166

Re: IOC device 9 (Sound Buffer Change)

Your thread makes interesting reading. If only I had some more time... but rammed with work and study until and of August. Two suggestions: 1) the way I implemented QTM's Transparent sound system may be useful to review here. It sits between the RISC OS Channel handler and SoundDMA. Works on Arthur ...
by steve3000
Sat Feb 22, 2014 1:10 am
Forum: Pi
Topic: Blitter support for VIDC1/20 and palette changes
Replies: 20
Views: 1212

Re: Blitter support for VIDC1/20 and palette changes

Great progress! Unfortunately I have very limited internet access right now as away from home. Just managed to get on here - I can't see where to download 237c, is that available anywhere? Although I'm using emulation only at moment... Have made some progress with LCDgm and thinking about your quest...
by steve3000
Fri Feb 14, 2014 12:37 am
Forum: Pi
Topic: Blitter support for VIDC1/20 and palette changes
Replies: 20
Views: 1212

Re: Blitter support for VIDC1/20 and palette changes

Good to hear! I've also made progress with LCDgm, hopefully have something out by end of month. As for palette table structure, this is important to get right as it will have a bearing on performance and flexibility. But I've also had a think about another option... Option 4... This could be flakey,...
by steve3000
Fri Feb 14, 2014 12:17 am
Forum: Pi
Topic: IOC emulation
Replies: 12
Views: 671

Re: IOC emulation

So...there's now no RPC emulators I can use to develop this as they all have fatal bugs. Aarrghhh! ahh yes... the joys of coding to the limit of emulation and beyond :) This doesn't of course explain the very similar random crash on the Pi, using Jahangir Khan as an example; if I change the interru...
by steve3000
Mon Feb 10, 2014 11:27 pm
Forum: Pi
Topic: IOC emulation
Replies: 12
Views: 671

Re: IOC emulation

Sorry, I meant to make that clearer in my description above. (1) is correct, all timers initialise to 0 at power on, so as soon as the Irq mask is cleared they will cause an interrupt. At power on, the RO rom is pulled low to address 0, its default Irq handler response is to mask out the timer inter...
by steve3000
Mon Feb 10, 2014 11:20 pm
Forum: Pi
Topic: Blitter support for VIDC1/20 and palette changes
Replies: 20
Views: 1212

Re: Blitter support for VIDC1/20 and palette changes

Good options! No. 2 is closest to what I have right now, but not necessarily the optimum. Let me think on this and run some tests.

256 colour mode with fixed palette - we can treat the same, I have some code to quickly convert from the 16 entry palette -> 256 colours, in 32bpp output.

Steve
by steve3000
Sat Feb 08, 2014 10:38 am
Forum: Pi
Topic: Blitter support for VIDC1/20 and palette changes
Replies: 20
Views: 1212

Re: Blitter support for VIDC1/20 and palette changes

Ok, looks good - so after I've sorted out LCDgm for VIDC20, I'll tidy up my 'blitter' module (which handles 1/2/4bpp to 32bpp with raster-level palette changes) and see if we can't patch this into the above ADFFS code and get mid-screen palette redefinitions going.
by steve3000
Sat Feb 08, 2014 10:25 am
Forum: LCDGameModes
Topic: LCDGameModes VIDC20
Replies: 10
Views: 866

Re: LCDGameModes VIDC20

Isn't that how LCDgm works anyhow? Game changes MODE, LCDgm patches it, game updates VIDC1. Yes, but in the back of my mind I thought that ADFFS cached the VIDC1 writes for translation, and fired them off together to VIDC20 at the same time? This would be slightly different behaviour. But we'll see...
by steve3000
Sat Feb 08, 2014 10:14 am
Forum: Pi
Topic: IOC emulation
Replies: 12
Views: 671

Re: IOC emulation

So on that basis - for IOC emulation, it's probably best to trigger the timer to start as soon as you've received the first T1 latch high and T1 latch low write. If you then receive a subsequent 'Go', reset the timer to the latch value.
by steve3000
Sat Feb 08, 2014 10:09 am
Forum: Pi
Topic: IOC emulation
Replies: 12
Views: 671

Re: IOC emulation

Could someone confirm my understanding of how IOC Timer 1 works You mean me ;) - sure 1. T1 Latch Low / High are written with the timer value 2. Bit 6 of IRQA mask is set to enable the IRQ 3. T1 Go is written to start the timer 4. IRQ is raised IRQ handler then does the following: 5. Bit 6 of IRQA ...